單片機(jī)設(shè)計外文翻譯

1、<p><b>　　畢業(yè)論文（設(shè)計）</b></p><p><b>　　外文翻譯</b></p><p>　　題 目： AT89C51單片機(jī) </p><p>　　系部名稱： 專業(yè)班級： </p>&l

2、t;p>　　學(xué)生姓名： 學(xué) 號： </p><p>　　指導(dǎo)教師： 教師職稱： 講師 </p><p>　　2012 年 3 月 9 日</p><p><b>　　AT89C51</b></p><p>　　

3、AT89C51是美國ATMEL公司生產(chǎn)的低電壓，高性能COMS8位單片機(jī)，片內(nèi)含4Kbytes的可反復(fù)擦寫的只讀程序存儲器（PEROM）和128bytes的隨機(jī)存取數(shù)據(jù)存儲器（RAM），器件采用ATMEL公司的高密度、非易失性存儲技術(shù)生產(chǎn)，兼容標(biāo)準(zhǔn)MCS-51指令系統(tǒng)，片內(nèi)置通用8位中央處理器（CPU）和Flash存儲單元，功能強(qiáng)大AT89C51單片機(jī)可為您提供許多高性價比的應(yīng)用場合，可靈活應(yīng)用于各種控制領(lǐng)域。</p>&

4、lt;p><b>　　主要性能參數(shù)：</b></p><p>　　·與MCS-51產(chǎn)品指令系統(tǒng)完全兼容</p><p>　　·4K字節(jié)可重擦寫Flash閃速存儲器</p><p>　　·1000次擦寫周期</p><p>　　·全靜態(tài)操作：0Hz—24MHz</p>

5、;<p>　　·三級加密程序存儲器</p><p>　　·128×8字節(jié)內(nèi)部RAM</p><p>　　·32個可編程I/O口線</p><p>　　·2個16位定時/計數(shù)器</p><p><b>　　·6個中斷源</b></p>

6、<p>　　·可編程串行UART通道</p><p>　　·低功耗空閑和掉電模式</p><p><b>　　功能特性概述：</b></p><p>　　AT89C51提供以下標(biāo)準(zhǔn)功能：4K字節(jié)Flash閃速存儲器，128字節(jié)內(nèi)部RAM，32個I/O口線，兩個16位定時/計數(shù)器，一個5向量兩級中斷結(jié)構(gòu)，一個全雙工串

7、行通信口，片內(nèi)振蕩器及時鐘電路。同時，AT89C51可降至0Hz的靜態(tài)邏輯操作，并支持兩種軟件可選的節(jié)電工作模式?？臻e方式停止CPU的工作，但允許RAM，定時/計數(shù)器。串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方式保存RAM中的內(nèi)容，但振蕩器停止工作并禁止其它所有部件工作直到下一個硬件復(fù)位。</p><p><b>　　引腳功能說明：</b></p><p><b>

8、;　　·VCC：電源電壓</b></p><p><b>　　·GND：地</b></p><p>　　·P0口：P0口是一組8位漏極開路型雙向I/O口，也即地址/數(shù)據(jù)總線復(fù)用口。作為輸出口用時，每位能吸收電流的方式驅(qū)動8個TTL邏輯門電路，對端口寫“1”可作為高阻抗輸入端用。</p><p>　　在訪

9、問外部數(shù)據(jù)存儲器或程序存儲器時，這組口線分時轉(zhuǎn)換地址（低8位）和數(shù)據(jù)總線復(fù)用，在訪問期間即或內(nèi)部上拉電阻。</p><p>　　在Flash編程時，P0口接收指令字節(jié)，而在程序校驗時，輸出指令字節(jié)，校驗時，要求外接上拉電阻。</p><p>　　·P1口：P1是一個帶有內(nèi)部上拉電阻的8位雙向I/O口，P1的輸出緩沖級可驅(qū)動（吸收或輸出電流）4個TTL邏輯門電路。對端口寫“1”，通

10、過內(nèi)部的上拉電阻把端口拉到高電平，此時可作輸入口。作輸入口使用時，因為內(nèi)部存在上拉電阻，某個引腳被外部信號拉低時會輸出一個電流（IIL）。</p><p>　　Flash編程和程序校驗期間，P1接收低8位地址。</p><p>　　·P2口：P2是一個帶有內(nèi)部上拉電阻的8位雙向I/O口，P2的輸出緩沖級可驅(qū)動（吸收或輸出電流）4個TTL邏輯門電路。對端口寫“1”，通過內(nèi)部的上拉電

11、阻把端口拉到高電平，此時可作輸入口。作輸入口使用時，因為內(nèi)部存在上拉電阻，某個引腳被外部信號拉低時會輸出一個電流（IIL）。</p><p>　　在訪問外部程序存儲器或16位地址的外部數(shù)據(jù)存儲器（例如執(zhí)行MOVX@DPTR指令）時，P2口送出高8位地址數(shù)據(jù)。在訪問8位地址的外部數(shù)據(jù)存儲器（如執(zhí)行MOVX@RI指令）時，P2口線上的內(nèi)容在整個訪問期間不改變。</p><p>　　Flash編

12、程或檢驗時，P2亦接收高位地址和其它控制信號。</p><p>　　·P3口：P3口是一組帶有內(nèi)部上拉電阻的8位雙向I/O口。P3口輸出緩沖級可驅(qū)動（吸收或輸出電流）4個TTL邏輯門電路。對P3口寫入“1”時，它們被內(nèi)部上拉電阻拉高并可作為輸入端口。作輸入端時，被外部拉低的P3口將用上拉電阻輸出電流（IIL）。</p><p>　　P3口還接收一些用于Flash閃速存儲器編程和程

13、序校驗的控制信號。</p><p>　　·RET：復(fù)位輸入。當(dāng)振蕩器工作時，RET引腳出現(xiàn)兩個機(jī)器周期以上高電平將使單片機(jī)復(fù)位。</p><p>　　·ALE/：當(dāng)訪問外部程序存儲器或數(shù)據(jù)存儲器時，ALE（地址鎖存允許）輸出脈沖用于鎖存地址的低8位字節(jié)。對Flash存儲器編程期間，該引腳還用于輸入編程脈沖（）。即使不訪問外部存儲器，ALE仍以時鐘振蕩頻率的1/6輸出固定

14、的正脈沖信號，因此它可對外輸出時鐘或用于定時目的。要注意的是：每當(dāng)訪問外部數(shù)據(jù)存儲器時將跳過一個ALE脈沖。</p><p>　　如有必要，可通過對特殊功能寄存器（SFR）區(qū)中的8EH單元的D0位置位，可禁止ALE操作。該位置位后，只有一條MOVX和MOVC指令A(yù)LE才會被激活。此外，該引腳會被微弱拉高，單片機(jī)執(zhí)行外部程序時，應(yīng)設(shè)置ALE無效。</p><p>　　·：程序儲存允

15、許（）輸出是外部程序存儲器的讀選通信號，當(dāng)AT89C51由外部程序存儲器取指令（或數(shù)據(jù)）時，每個機(jī)器周期兩次有效，即輸出兩個脈沖。在此期間，當(dāng)訪問外部數(shù)據(jù)存儲器，這兩次有效的信號不出現(xiàn)。</p><p>　　EA/VPP：外部訪問允許。欲使CPU僅訪問外部程序存儲器（地址為0000H—FFFFH），EA端必須保持低電平（接地）。需注意的是：如果加密位LB1被編程，復(fù)位時內(nèi)部會鎖存EA端狀態(tài)。如EA端為高電平（接V

16、CC端），CPU則執(zhí)行內(nèi)部程序存儲器中的指令。</p><p>　　Flash存儲器編程時，該引腳加上+12V的編程允許電源VPP，當(dāng)然這必須是該器件是使用12V編程電壓VPP。</p><p>　　XTAL1：振蕩器反相放大器及內(nèi)部時鐘發(fā)生器的輸入端。</p><p>　　XTAL2：振蕩器反相放大器的輸出端。</p><p>　　Read

17、y/：字節(jié)編程的進(jìn)度可通過RDY/輸出信號監(jiān)測，編程期間，ALE變?yōu)楦唠娖健癏”后P3.4（RDY/）端電平被拉低，表示正在編程狀態(tài)（忙狀態(tài)）。編程完成后，P3.4變?yōu)楦唠娖奖硎緶?zhǔn)備就緒狀態(tài)。</p><p><b>　　時鐘振蕩器：</b></p><p>　　AT89C51中有一個用于構(gòu)成內(nèi)部振蕩器的高增益反相放大器，引腳XTAL1和XTAL2分別是該放大器的輸入

18、端和輸出端。這個放大器與作為反饋元件的片外石英晶體 或陶瓷諧振器一起構(gòu)成自激振蕩器。</p><p>　　用戶也可以采用外部時鐘。這種情況下，外部時鐘脈沖接到XTAL1端，即內(nèi)部時鐘發(fā)生器的輸入端，XTAL2則懸空。</p><p>　　由于外部時鐘信號是通過一個2分頻觸發(fā)器后作為內(nèi)部時鐘信號的，所以對外部時鐘信號的占空比沒有特殊要求，但最小高電平持續(xù)時間和最大的低電平持續(xù)時間應(yīng)符合產(chǎn)品技

19、術(shù)條件的要求。</p><p><b>　　空閑節(jié)電模式：</b></p><p>　　在空閑工作模式狀態(tài)，CPU保持睡眠狀態(tài)而所有片內(nèi)的外設(shè)仍保持激活狀態(tài)，這種方式由軟件產(chǎn)生。此時，片內(nèi)RAM和所有特殊功能寄存器的內(nèi)容保持不變?？臻e模式可由任何允許的中斷請求或硬件復(fù)位終止。</p><p>　　通過硬件復(fù)位也可將空閑工作模式終止。需要注意的是

20、：當(dāng)由硬件復(fù)位來終止空閑工作模式時，CPU通常是從激活空閑模式那條指令的下一條指令開始繼續(xù)執(zhí)行程序的，要完成內(nèi)部復(fù)位操作，硬件復(fù)位脈沖要保持兩個機(jī)器周期有效，在這種情況下，內(nèi)部禁止CPU訪問片內(nèi)RAM，而允許訪問其它端口。為了避免可能對端口產(chǎn)生意外寫入，激活空閑模式的那條指令后一條指令不應(yīng)是一條對端口或外部存儲器的寫入指令。</p><p><b>　　掉電模式：</b></p>

21、<p>　　在掉電模式下，振蕩器停止工作，進(jìn)入掉電模式的指令是最后一條被執(zhí)行的指令，片內(nèi)RAM和特殊功能寄存器的內(nèi)容在終止掉電模式前被凍結(jié)。退出掉電模式的唯一方法是硬件復(fù)位，復(fù)位后將重新定義全部特殊功能寄存器但不改變RAM中的內(nèi)容，在VCC恢復(fù)到正常工作電平前，復(fù)位應(yīng)無效，且必須保持一定時間以使振蕩器重啟動并穩(wěn)定工作。</p><p><b>　　程序存儲器的加密：</b>&l

22、t;/p><p>　　當(dāng)加密位LB1被編程時，在復(fù)位期間，EA端的邏輯電平被采樣并鎖存，如果單片機(jī)上電后一直沒有復(fù)位，則鎖存起的初始值是一個隨機(jī)數(shù)，且這個隨機(jī)數(shù)會一直保存到真正復(fù)位為止。為使單片機(jī)能正常工作，被鎖存的EA電平值必須與該引腳當(dāng)前的邏輯電平一致。此外，加密位只能通過整片擦除的方法清除。</p><p>　　Flash閃速存儲器的編程：</p><p>　　A

23、T89C51單片機(jī)內(nèi)部有4K字節(jié)的Flash PEROM，這個Flash存儲陣列出廠時已處于擦除狀態(tài)（即所有存儲單元的內(nèi)容均為FFH），用戶隨時可對其進(jìn)行編程。編程接口可接收高電壓（+12V）或低電壓（VCC）的允許編程信號。低電壓編程模式適合于用戶在線編程系統(tǒng)，而高電壓編程模式可與通用EPROM編程器兼容。</p><p>　　AT89C51的程序存儲器陣列是采用字節(jié)寫入方式編程的，每次寫入一個字節(jié)，要對整個芯

24、片內(nèi)的PEROM程序存儲器寫入一個非空字節(jié)，必須使用片擦除的方式將整個存儲器的內(nèi)容清除。</p><p><b>　　編程方法：</b></p><p>　　編程前，須根據(jù)表設(shè)置好地址、數(shù)據(jù)及控制信號。AT89C51編程方法如下：</p><p>　　1、在地址線上加上要編程單元的地址信號。</p><p>　　2、在數(shù)

25、據(jù)線上加上要寫入的數(shù)據(jù)字節(jié)。</p><p>　　3、激活相應(yīng)的控制信號。</p><p>　　4、在高電壓編程方式時，將EA/VPP端加上+12V編程電壓。</p><p>　　5、每對Flash存儲陣列寫入一個字節(jié)或每寫入一個程序加密位，加上一個ALE/編程脈沖。改變編程單元的地址和寫入的數(shù)據(jù)，重復(fù)1—5步驟，直到全部文件編程結(jié)束。每個字節(jié)寫入周期是自身定時的，

26、通常約為1.5ms。</p><p><b>　　數(shù)據(jù)查詢：</b></p><p>　　AT89C51單片機(jī)用數(shù)據(jù)查詢方式來檢測一個寫周期是否結(jié)束，在一個寫周期中，如需讀取最后寫入的那個字節(jié)，則讀出的數(shù)據(jù)最高位是原來寫入字節(jié)最高位的反碼。寫周期完成后，有效的數(shù)據(jù)就會出現(xiàn)在所有輸出端上，此時，可進(jìn)入下一個字節(jié)的寫周期，寫周期開始后，可在任意時刻進(jìn)行數(shù)據(jù)查詢。</

27、p><p><b>　　程序校驗：</b></p><p>　　如果加密位LB1、LB2沒有進(jìn)行編程，則代碼數(shù)據(jù)可通過地址和數(shù)據(jù)線讀回原編寫的數(shù)據(jù)。加密位不可直接校驗，加密位的校驗可通過對存儲器的校驗和寫入狀態(tài)來驗證。</p><p><b>　　芯片擦除：</b></p><p>　　利用控制信號的正

28、確組合并保持ALE/引腳10ms的低電平脈沖寬度即可將PEROM陣列（4K字節(jié)）和三個加密位整片擦除，代碼陳列在片擦除操作中將任何非空單元寫入“1”，這步驟需再編程之前進(jìn)行。</p><p><b>　　讀片內(nèi)簽名字節(jié)：</b></p><p>　　讀簽名字節(jié)的過程和單元030H、031H及032H的正常校驗相仿，只需將P3.6和P3.7保持低電平，返回值意義如下：&

29、lt;/p><p>　　(030H)=1EH聲明產(chǎn)品由ATMEL公司制造</p><p>　　(031H)=51H聲明為AT89C51單片機(jī)</p><p>　　(032H)=FFH聲明為12V編程電壓</p><p>　　(032H)=05H聲明為5V編程電壓</p><p><b>　　編程接口：</b

30、></p><p>　　采用控制信號的正確組合可對Flash閃速存儲陣列中的每一代碼字節(jié)進(jìn)行寫入和存儲器的整片擦除，寫操作周期是自身定時的，初始化后它將自動定時到操作完成。</p><p><b>　　AT89C51</b></p><p>　　The AT89C51 is a low-power, high-performance CM

31、OS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM) and 128 bytes of data random-access memory(RAM). The device is manufactured using ATMEL Co.’s high-density nonvolatile memo

32、ry technology and is compatible with the industry-standard MCS-51 instruction set and pin-out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer.

33、By combining </p><p><b>　　Features:</b></p><p>　　·Compatible with instruction set of MCS-51 products</p><p>　　·4K bytes of in-system reprogrammable Flash memor

34、y</p><p>　　·Endurance: 1000 write/erase cycles</p><p>　　·Fully static operation: 0 Hz to 24 MHz</p><p>　　·Three-level program memory lock</p><p>　　·

35、128×8-bit internal RAM</p><p>　　·32 programmable I/O lines</p><p>　　·Two 16-bit Timer/Counters</p><p>　　·Six interrupt source</p><p>　　·Program

36、mable serial channel</p><p>　　·Low-power idle and Power-down modes</p><p>　　Function Characteristic Description:</p><p>　　The AT89C51 provides the following standard features:

37、4K bytes of Flash memory, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT

38、89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and inte

39、rrupt </p><p>　　Pin Description:</p><p>　　·VCC: Supply voltage</p><p>　　·GND: Ground</p><p>　　·Port 0: Port 0 is an 8-bit open-drain bi-directional I/O p

40、ort. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs.</p><p>　　Port 0 may also be configured to be the multiplexed low

41、 order address/bus during accesses to external program and data memory. In this mode P0 has internal pull ups. </p><p>　　Port 0 also receives the code bytes during Flash programming, and outputs the code byt

42、es during program verification. External pull ups are required during program verification.</p><p>　　·Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull ups. The Port 1 output buffers

43、can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current

44、 (IIL) because of the internal pull ups. </p><p>　　Port 1 also receives the low-order address bytes during Flash programming and verification.</p><p>　　·Port 2: Port 2 is an 8-bit bi-direct

45、ional I/O port with internal pull ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Por

46、t 2 pins that are externally being pulled low will source current (IIL) because of the internal pull ups.</p><p>　　Port 2 emits the high-order address byte during fetches from external program memory and dur

47、ing accesses to external data memory which uses 16-bit addresses (MOVX @ DPTR). In this application, it uses strong internal pull ups when emitting 1s. During accesses to external data memory which uses 8-bit addresses (

48、MOVX @ RI). Port 2 emits the contents of the P2 Special Function Register.</p><p>　　Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.</p&

49、gt;<p>　　·Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pull ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the i

50、nternal pull ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull ups.</p><p>　　Port 3 also receives some control signals f

51、or Flash programming and verification.</p><p>　　·RST: Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.</p><p>　　·ALE/: Address

52、Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input () during Flash programming. In normal operation ALE is emitted at a constan

53、t rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.</p><p>　　If desired,

54、 ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no ef

55、fect if the microcontroller is in external execution mode.</p><p>　　·：Program Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory,

56、 is activated twice each machine cycle, except that two activations are skipped during each access to external data memory.</p><p>　　·EA/VPP：External Access Enable. EA must be strapped to GND in order

57、 to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to

58、VCC for internal program executions. </p><p>　　This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.</p><p>　　·XT

59、AL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.</p><p>　　·XTAL2：Output from the inverting oscillator amplifier.</p><p>　　·Ready/: The

60、 progress of byte programming can also be monitored by the RDY/output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate REA

61、DY.</p><p>　　Oscillator Characteristics：</p><p>　　XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator. Eith

62、er a quartz crystal or ceramic resonator may be used. </p><p>　　To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven.</p><p>　　There are no r

63、equirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide by two flip trigger, but minimum and maximum voltage high and low time specifications mus

64、t be observed.</p><p>　　Idle Mode：</p><p>　　In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chi

65、p RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.</p><p>　　It should be noted that when idle is

66、 terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to inte

67、rnal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idl

68、e should not be one that</p><p>　　Power-down Mode:</p><p>　　In the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The o

69、n-chip RAM and special function registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the special function registers but does not change

70、 the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to al</p><p>　　Program Memory Lock Bits:</p><p>　　Whe

71、n lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is act

72、ivated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.</p><p>　　Programming the Flash:</p><p>

73、;　　The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-

74、voltage (VCC) program enable signal. The low-voltage programming mode provides a convenient way to program the AT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional thi

75、rd party Flash or EPROM programmers.The AT89C51 is shipped with</p><p>　　The AT89C51 code memory array is programmed byte-by-byte in either programming mode. To program any nonblank byte in the on-chip Flash

76、 memory, the entire memory must be erased using the chip erase mode. </p><p>　　Programming Algorithm: </p><p>　　Before programming the AT89C51, the address, data and control signals should be se

77、t up according to the Flash programming mode table .To program the AT89C51, take the following steps:</p><p>　　1. Input the desired memory location on the address lines.</p><p>　　2. Input the ap

78、propriate data byte on the data lines.</p><p>　　3. Activate the correct combination of control signals.</p><p>　　4. Raise EA/VPP to 12V for the high-voltage programming mode.</p><p>

79、;　　5. Pulse ALE/once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5ms. Repeat steps 1 through 5, changing the address and data for the entir

80、e array or until the end of the object file is reached.</p><p>　　Data Polling: </p><p>　　The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempte

81、d read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data polling may begi

82、n any time after a write cycle has been initiated.</p><p>　　Program Verify: </p><p>　　If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address

83、 and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.</p><p>　　Chip Erase: </p><p>

84、　　The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/ low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed bef

85、ore the code memory can be re-programmed.</p><p>　　Reading the Signature Bytes:</p><p>　　The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and

86、032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows:</p><p>　　(030H) = 1EH indicates manufactured by ATMEL</p><p>　　(031H) = 51H indicates AT89C51 s

87、ingle-chip</p><p>　　(032H) = FFH indicates 12V programming</p><p>　　(032H) = 05H indicates 5V programming</p><p>　　Programming Interface:</p><p>　　Every code byte in th

88、e Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is self timed and once initiated, will automatically time itself to compl