單片機設計外文翻譯---單片機工作原理

1、<p>　　中文2970字，1825單詞</p><p><b>　　附 錄</b></p><p><b>　　一、英文原文:</b></p><p>　　The Principle of Microcontroller</p><p>　　In operation the Singl

2、e Chip Microcomputer (SCM)is connected to a host PC microcomputer via aserial port. The connecting cable is included with the unit.</p><p>　　The SCM is supplied fitted with an 8751 chip. This chip features i

3、nternal ROM containing versatile,real time monitor to communicate with a PC via the built-in serial port. The monitor includes a line assembler, disassembler, break points, single stepping and the facility to examine and

4、 exchange memory or register contents.</p><p>　　A special function of the monitor is to store the program under development in the RAM of the SCM development board. The great advantage of the method that is

5、direct access to the I/O ports is provided by the 8051 is retained and, consequently,the need for a costly in-circuit-emulation (ICE)package is not required.</p><p>　　Once a program has been completed on the

6、 SCM development system it can be easily transferred intothe ROM of another 8751 via an EPROM programmer. This second 8751, now containing the control program, can be removed from the Programmer and installed into the SC

7、M-TB target board. Most importantly, because direct access to the input/output ports of the 8751 has been retained during the development stage there is no need for peripheral I/O and address decoding chips; only the8751

8、 chip is required. T</p><p>　　The SCM-TB target board feature a single 40-wayDIL socket for the micro-controller chip plus termination facilities identical to the SCMDevelopment Board for simple and convenie

9、nt transfer of any connecting cables. 8751 ICS should be purchased separately for the target board.In addition to the Single Chip Development System and Target Board, a number of add-on boards are available. These includ

10、e a Port Monitor Board,Multi-Channel ADC, Screw Terminal Board andOutput Driver Board.</p><p>　　Voice input to a machine is the most natural form of man-machine communications. Research coming to fruition ov

11、erthe past several years indicates that the techniques of manmachine communication by voice constitute a whole new range of communication services—services that can extend man's capabilities, serve his social needs,

12、and increase his productivitySpeech recognition can be defined as the technology which makes it possible for a computer to accept voice dataas input and then identify the wo</p><p>　　(1) It is an easier mean

13、s for noncomputer professionals toenter data into the computer.</p><p>　　(2) In certain applications, such as in semiautomatedquality-control inspection procedures, computer usersneed to use their hands for

14、other tasks. Speech recognition is a part of a broader speech processingtechnology involving computer identification or verification of speakers, computer synthesis of speech, production ofstoredspokenresponses,computer

15、analysis of the physicaland psychological state of </p><p>　　the speaker, efficienttransmission of spoken conversations, detection of speechpathologies, and aids to the handicapped , taking machinestalk and

16、listen to humans depends upon economical implementationof speech synthesis and speech recognition.A number of different feature sets have been proposedto represent speech signals; these include energy and zerocrossing ra

17、tes, formant filtering, short time spectrum,waveform digitization and linear predictive coding (LPC).</p><p>　　The motivation for choosing one feature set over another isoften complex and highly dependent an

18、 constraints imposedupon the system, e.g., cost, speed, response time, computationalcomplexity, etc- Of all the many available feature sets, linear predictive coding is usually the most effectiveone .</p><p>

19、;　　There are many classifications for computers, ranging from inexpensive microcomputers used in homes and offices, to liquid-cooled supercomputers used in universities and research laboratories. The present invention re

20、lates to microcomputers, also known as "personal computers" (or "PCs"). </p><p>　　A microcomputer can be defined as a "computer having a mass-produced integrated circuit microprocess

21、or", such as, for example, the Intel 80×86 family of products which presently includes the 8086, 80286, 80386 and 80486 microprocessors. Although the microprocessor is the heart and defining feature of a microc

22、omputer, it is not very useful unless it is integrated with a memory and a set of input/output ("I/O") devices, also known as peripherals. These three classes of devices communicate among th</p><p>

23、;　　The bus is logically organized into sets of address, data, and control lines. The address lines are for communicating device addresses which uniquely identify a particular device on the bus. The data lines are for com

24、municating binary data between two bus devices, a bus master, which initiates a data transfer by placing an address on the address lines, and a bus slave, which reads and decodes the address generated by the bus master a

25、s its own. The control lines are for coordinating access to the</p><p>　　memory to be read by placing the proper logic level on a write/read control line. In this way, the microprocessor gains access to the

26、data stored in the memory location specified by the logic levels placed on the address lines by the microprocessor. </p><p>　　A bus cycle begins when the bus master directs a write or a read on the bus. The

27、bus cycle is completed after all data has been transferred across the bus and the bus master releases control of the bus. If the two devices communicating with each other over the bus operate at the same speed, then a bu

28、s cycle may be achieved over a minimum number of clock cycles. If, on the other hand, a bus device can only transmit or receive data over many clock cycles, then a delay must be injected into the sta</p><p>

29、　　Buses may be generally classified as synchronous or asynchronous, where synchronous buses are distinguished by the requirement that all bus devices synchronize their use of the bus by a single clock source (or a fundam

30、ental frequency). An example of a synchronous bus used in a microcomputer is the IBM PC AT I/O Channel, AT-bus or Industry Standard Architecture bus ("ISA-bus"). Present bus frequency standards for the ISA-bus

31、are 8 MHz and 10 MHz. </p><p>　　The ISA-bus, an example of a synchronous bus, is used with the Intel 80386 microprocessor. The ISA-bus provides a 16-bit data bus and a 24-bit address bus. For purposes of thi

32、s discussion, the control lines of the ISA-bus include four bus cycle definition lines. The bus cycle definition lines define the type of bus cycle being performed. (In the following definitions, and throughout the remai

33、nder of this patent document, all signal names that are terminated with an asterisk [*] indicate an activ</p><p>　　In addition to the above-mentioned bus cycle definition signals there are some microprocesso

34、r specific signals that are used in most microcomputers for specifically interfacing the Intel 80×86 microprocessor family. There are two bus control signals and two bus arbitration signals of particular importance

35、for bus interfacing. The bus control signals allow the microprocessor to indicate when a bus cycle has begun, and allows other bus devices to indicate a bus cycle termination. The address statu</p><p>　　One

36、skilled in the technology will understand the operation of the ISA-bus, other applicable industry standard buses, and the Intel 80×86 microprocessor family. At least two references are available on the subject inclu

37、ding The IBM PC from the Inside Out, Revised Edition, by Murray Sargent III and Richard L. Shoemaker; and IBM PC AT Technical Reference published by IBM Corporation. </p><p>　　Synchronous buses are ordinaril

38、y preferred for microcomputers since they can often transfer data faster than asynchronous buses. Certain applications, however, especially where lengthy communication distances are involved, require asynchronous or &quo

39、t;handshake only" type buses. When devices are separated by some distance, the same phase transition of a common clock cannot be guaranteed. </p><p>　　The primary disadvantage of the synchronous ISA-bus

40、 has only recently been recognized. Basically, microcomputers are evolving down two separate paths of variables: one set of variables is associated with the bus design and the other set is associated with the microproces

41、sor and memory designs. A synchronous bus, such as the ISA-bus, should remain constant so that microcomputers in a single product line are all compatible. That is, a peripheral such as a modem, printer and so on will ope

42、rate thro</p><p>　　In contrast, microprocessor and memory technologies are rapidly evolving in functionality and performance. For example, the microprocessor changes in architectural definition (e.g., number

43、 of pins, instruction sets, etc.) and clock frequency (e.g., 16 MHz, 25 MHz, 33 MHz), the cache becomes more sophisticated, coprocessors become a part of the microcomputer architecture (e.g., Intel 80387 numeric coproces

44、sor), and main memory becomes faster. </p><p>　　As an example of memory evolution, consider dynamic random access memory, or "DRAM". As DRAM technology improves, the opportunity for improved system

45、 performance becomes clear. In the early days of personal computers, the common DRAM chip being used in microcomputers was 64K×1 (65,536×1 bits), having an access time of 150 nanoseconds. Recently, a standard (

46、i.e., readily available and cost effective) DRAM size used by microcomputer manufacturers was 256K×1, having an access time of 100 nanosecond</p><p>　　It is desireable to isolate the memory and micropro

47、cessor from the synchronous I/O bus design so that different DRAM and microprocessors at different operating frequencies can be used without affecting the synchronous I/O bus design. Otherwise, if the synchronous bus is

48、not isolated from the computation and storage elements, each technological improvement in memory or microprocessor products will require unique interface circuitry to scale-down communication speed with other devices acr

49、oss the s</p><p>　　Consequently, a need exists for improvements in microcomputer systems to isolate I/O channel design from memory and microprocessor designs. </p><p><b>　　二、英文翻譯：</b>

50、;</p><p><b>　　單片機工作原理</b></p><p>　　在通過端口把單片機連接到個人電腦上的操作中連接電纜也包含在這個系統中。 單片機安裝有一個8751芯片,這個芯片內部的ROM包含多種功能.實時監(jiān)控器通過PC的串行端口進行聯系。監(jiān)控器包含一個行匯編，反匯編，斷點，單步和檢驗及存儲器、寄存器間內容進行交換的設備。 監(jiān)控器的一個特殊功能是存儲

51、單片機開發(fā)板RAM中的程序。該方法的優(yōu)點是直接進入到由8051保存的I / O端口，因此，一個昂貴的電路仿真（ICE）包是不必需的。</p><p>　　一旦單片機開發(fā)系統方案已經完成便可以輕松地通過一個EPROM將程序轉移到另一個8751ROM。第二個8751芯片現在包含控制程序，可以從程序編程器中移除并且安裝到單片機。最重要的，因為直接訪問輸入/輸出端口的8751一直保留在開發(fā)階段，因此外圍I / O和地址解

52、碼芯片是不需要的，只有8751芯片是必需的。因此，單片機控制，不是多芯片控制得以實現。</p><p>　　單片機集成板的特點為微控制器芯片與單片機的終端設備都為40 wayDIL插座。板子的開發(fā)為電纜連接更加簡單方便。8751 ICS應該是單獨購買。除了單片機開發(fā)系統和目標板，一系列附加板子是單獨提供的這些包括端口顯示器，多通道ADC，螺絲終端板和輸出驅動板。</p><p>　　將語音

53、輸入到一臺計算機是人機通信最原始的形式。過去幾年來的研究成果表明，通過聲音進行人機通信的技術成為了一項全新的通信服務技術，這項服務可以提高人的能力，為社會服務，并提高生產力。</p><p>　　語音識別可以被定義為一種把聲音數據作為輸入并能辨別單詞和語法的技術。</p><p>　　語音識別系統有兩方面的優(yōu)點：</p><p>　?。?）它是一種非常簡單的技術手段

54、，非專業(yè)的計算機人員也可以把數據輸入電腦。</p><p>　?。?）在某些應用方面，如半自動質量控制檢查程序，計算機用戶需要去做其它方面的任務。語音識別是更廣泛的語音處理技術的一部分，它涉及電腦技術鑒定或對語音輸入的核實，電腦語音合成，對已存儲語音的反應，計算機的物理分析和對聲音輸入者心理狀態(tài)的分析，高效率傳輸口語對話，語音檢測，采取機器語言，并聽取人類的口令依靠的是綜合語音應用系統和語音識別。</p&g

55、t;<p>　　體現語音信號的許多不同特征已經被提出。這些包括能源和零交叉率，共振峰濾波，短時譜，波形數字化和線性預測編碼（LPC）等。選擇一個功能較另一組的動機往往是很復雜的，它受限于系統。如成本，速度，反應時間，電腦的復雜程度等-所有可以考慮的特征。</p><p>　　有很多分類的計算機，從家庭和辦公室使用的廉價的微型計算機，到在大學和研究實驗室使用的液體冷卻的超級計算機。本發(fā)明涉及微型計算機

56、，也稱為“個人電腦”。</p><p>　　微機可被定義為一個“由一個大規(guī)模的集成電路組成的微處理器”，例如英特爾80 × 86的產品家族，目前包括8086，80286，80386和80486微處理器。雖然微處理器是微機的核心和主要特征，但它不是很有用，除非它和內存還有輸入輸出端口集成在一起，這三類設備間進行通信是在一個共享的數字信號線上稱為總線。</p><p>　　總線在邏輯

57、上是由一系列的地址，數據和控制線構成。地址線是在總線上唯一被確定的通信設備的地址。數據線是在兩個總線設備間傳送二進制數據，總線主機是通過放置地址總線的一個地址進行數據轉換，總線附屬是讀取和解碼。把總線主機產生的地址作為自己的地址?？刂瓶偩€是協調總線入口和選擇一個操作總線的合適模式，例如數據輸入模式和數據讀出模式。例如，如果總線主機是微處理器，總線附屬是一個內存，微處理器的內存可直接被讀出通過在讀寫控制線上找尋合適的邏輯電平。這樣，微處理

58、器能夠訪問由微處理器的地址線的邏輯電平確定的存儲單元中存儲的數據。</p><p>　　當總線主機開始在總線上的讀寫時一個總線周期便開始了。當所有數據在總線上翻譯后總線周期釋放了對總線的控制一個總線周期便完成了，如果兩個設備通過總線操作以相同的速度進行通信，那么總線周期可能會用最小的周期。如果，另一方面，總線設備只能發(fā)送或接收數據的時鐘周期，那么速度相對較快的設備必須進行延遲。在這種情況下，已經就緒的控制線通常是

59、由慢的裝置啟動然后指示相對較快的設備總線可以使用或已經從總線接受了數據。</p><p>　　總線一般可劃分為同步或異步，同步總線是由同一時鐘源下所有總線設備同時使用總線來區(qū)別的（或基本頻率）。微機中一個同步總線的例子是IBM個人電腦的I / O通道。目前總線的ISA總線頻率標準是8兆赫和10兆赫。 </p><p>　　ISA總線，同步總線一個的例子，用作Intel 80386的微處理器

60、。在ISA總線提供了一個16位數據總線和24位地址總線。對于本次討論目的，ISA總線的控制線，包括4個總線周期的定義線。該總線周期定義線定義了總線周期的類型。 當數據從內存中讀出時一個總線周期定義線調用內存讀取（“MEMR *”）。當總數據被寫入內存時一個總線周期定義行調用存儲器寫（“MEMW *”）。當數據從外圍設備讀入時一個總線周期定義行調用I / O讀（“提高采收率*”）。當數據寫入外圍設備時一個總線周期定義行調用的I / O寫。

61、</p><p>　　除了上述總線周期定義信號，還有一些用于大多數微機專門接口的英特爾處理器的80 × 86系列微處理器的特定信號。有兩種總線控制信號和兩種對總線接口尤為重要的仲裁信號。當總線周期開始的時候總線控制信號允許微處理器給出指示。地址狀態(tài)信號表明，一個有效的總線周期的定義和地址由80386微處理器的輸出引腳驅動。當轉移確認（“待用*”）的信號時表明當前總線周期完成。</p>&l

62、t;p>　　一個熟練掌握這項技術的人將了解ISA總線的運行，其他適用的行業(yè)標準總線，以及80 × 86的英特爾微處理器家族，至少兩個都可以用于這個課題的參考，包括有 Murray Sargent III 和 Richard L. Shoemaker出版的修訂版還有由IBM公司出版的IBM電腦技術參考。</p><p>　　同步總線通常首選微型計算機，因為它的數據傳輸速度比異步總線快。但是，某些應用

63、尤其是長距離的通信，需要異步或“握手”式的總線。當設備被分開一段距離，時鐘同相變不能得到保證。</p><p>　　同步ISA總線的主要缺點最近才被認識到。基本上，微型計算機正在形成兩條不同路徑的變量：一組變量是與總線的設計和其他與微處理器和存儲器的設計相關的設置。一個同步總線，如ISA總線，應保持穩(wěn)定，以便使微機在單一的生產線上兼容。也就是說，外圍設備如調制解調器，打印機將通過在總線定義下的時鐘頻率控制器下運行

64、。因此，總線應通過符合相同規(guī)范的更有效的設計進行改變。例如，總線的工作頻率應保持不變，以保證所有外圍設備正確操作與總線標準一致。</p><p>　　相比之下，微處理器和存儲技術的性能和功能正在迅速發(fā)展中。例如，微處理器在結構定義方面的變化（例如，引腳數，指令集等）和時鐘頻率（例如，16兆赫，25兆赫，33兆赫），緩存變得更加復雜，協處理器成為微機體系結構的一部分（例如，英特爾80387數字協處理器），主內存變得

65、更快。</p><p>　　作為內存發(fā)展的例子，考慮動態(tài)隨機存儲器，或“內存”。隨著DRAM技術的發(fā)展，為提高系統性能的機會就很清楚了。在個人電腦發(fā)展的初期，微型計算機用的是64K的× 1（65,536 × 1位）的動態(tài)隨機存儲器，有1 150納秒存取時間。最近，一個標準內存大小256K的微機制造商使用的是× 1，有1 100納秒存取時間。目前，一個標準的80納秒或更少的存取的1M*

66、1DRAM芯片正在演變?yōu)橐粋€商業(yè)上可行的標準，而技術趨勢是1600萬的一位芯片。</p><p>　　把內存和微處理器從同步輸入輸出端口總線設計中分離出來是可取的，這樣在不同操作頻率下工作的不同的動態(tài)隨機存儲器和微處理器可以在不影響同步輸入輸出端口總線設計的情況下使用。否則，如果同步總線沒有從計算和存儲單元中分離，每個存儲器或微處理器技術的進步都需要特有的接口電路，用來擴展同步通信總線上的其他設備的速度。因此，微