電氣類外文翻譯---數(shù)字信號處理控制器

1、<p><b>　　文獻翻譯</b></p><p>　　TMS320LF2407, TMS320LF2406, TMS320LF2402</p><p>　　TMS320LC2406, TMS320LC2404, MS320LC2402</p><p>　　DSP CONTROLLERS</p><p>　　

2、The TMS320LF240x and TMS320LC240x devices, new members of the ’24x family of digital signal processor (DSP) controllers, are part of the C2000 platform of fixed-point DSPs. The ’240x devices offer the enhanced TMS320 arc

3、hitectural design of the ’C2xx core CPU for low-cost, low-power, high-performance processing capabilities. Several advanced peripherals, optimized for digital motor and motion control applications, have been integrated t

4、o provide a true single chip DSP controller. While code-comp</p><p>　　The ’240x family offers an array of memory sizes and different peripherals tailored to meet the specific price/performance points require

5、d by various applications. Flash-based devices of up to 32K words offer a reprogrammable solution useful for:</p><p>　　Applications requiring field programmability upgrades.</p><p>　　Development

6、 and initial prototyping of applications that migrate to ROM-based devices.</p><p>　　Flash devices and corresponding ROM devices are fully pin-to-pin compatible. Note that flash-based devices contain a 256-w

7、ord boot ROM to facilitate in-circuit programming.</p><p>　　All ’240x devices offer at least one event manager module which has been optimized for digital motor control and power conversion applications. Cap

8、abilities of this module include centered- and/or edge-aligned PWM generation, programmable deadband to prevent shoot-through faults, and synchronized analog-to-digital conversion. Devices with dual event managers enable

9、 multiple motor and/or converter control with a single ‘240x DSP controller.</p><p>　　The high performance, 10-bit analog-to-digital converter (ADC) has a minimum conversion time of 500 ns and offers up to

10、16 channels of analog input. The auto sequencing capability of the ADC allows a maximum of 16 conversions to take place in a single conversion session without any CPU overhead.</p><p>　　A serial communicatio

11、ns interface (SCI) is integrated on all devices to provide asynchronous communication to other devices in the system. For systems requiring additional communication interfaces; the ’2407, ’2406, and ’2404 offer a 16-bit

12、synchronous serial peripheral interface (SPI). The ’2407 and ’2406 offer a controller area network (CAN) communications module that meets 2.0B specifications. To maximize device flexibility, functional pins are also conf

13、igurable as general purpose inputs/outp</p><p>　　To streamline development time, JTAG-compliant scan-based emulation has been integrated into all devices. This provides non-intrusive real-time capabilities r

14、equired to debug digital control systems. A complete suite of code generation tools from C compilers to the industry-standard Code Composerdebugger supports this family. Numerous third party developers not only offer dev

15、ice-level development tools, but also system-level design and development support.</p><p>　　PERIPHERALS</p><p>　　The integrated peripherals of the TMS320x240x are described in the following subs

16、ections: </p><p>　　1Two event-manager modules (EVA, EVB)</p><p>　　2Enhanced analog-to-digital converter (ADC) module</p><p>　　3Controller area network (CAN) module</p><p&

17、gt;　　3Serial communications interface (SCI) module</p><p>　　4Serial peripheral interface (SPI) module</p><p>　　5PLL-based clock module</p><p>　　6Digital I/O and shared pin functions

18、</p><p>　　7External memory interfaces (’LF2407 only)</p><p>　　8Watchdog (WD) timer module</p><p>　　Event manager modules (EVA, EVB)</p><p>　　The event-manager modules i

19、nclude general-purpose (GP) timers, full-compare/PWM units, capture units, and quadrature-encoder pulse (QEP) circuits. EVA’s and EVB’s timers, compare units, and capture units function identically. However, timer/unit n

20、ames differ for EVA and EVB. Table 1 shows the module and signal names used. Table 1 shows the features and functionality available for the event-manager modules and highlights EVA nomenclature. </p><p>　　Ev

21、ent managers A and B have identical peripheral register sets with EVA starting at 7400h and EVB starting at 7500h. The paragraphs in this section describe the function of GP timers, compare units, capture units, and QEPs

22、 using EVA nomenclature. These paragraphs are applicable to EVB with regard to function—however, module/signal names would differ. </p><p>　　Table 1. Module and Signal Names for EVA and EVB</p><p&

23、gt;　　General-purpose (GP) timers</p><p>　　There are two GP timers: The GP timer x (x = 1 or 2 for EVA; x = 3 or 4 for EVB) includes:</p><p>　　1.A 16-bit timer, up-/down-counter, TxCNT, for reads

24、 or writes</p><p>　　2.A 16-bit timer-compare register, TxCMPR (double-buffered with shadow register), for reads or writes</p><p>　　3.A 16-bit timer-period register, TxPR (double-buffered with s

25、hadow register), for reads or writes</p><p>　　4.A 16-bit timer-control register,TxCON, for reads or writes</p><p>　　5.Selectable internal or external input clocks</p><p>　　6.A progr

26、ammable prescaler for internal or external clock inputs</p><p>　　7.Control and interrupt logic, for four maskable interrupts: underflow, overflow, timer compare, and period interrupts</p><p>　　8

27、.A selectable direction input pin (TDIR) (to count up or down when directional up-/down-count mode is selected)</p><p>　　The GP timers can be operated independently or synchronized with each other. The compa

28、re register associated with each GP timer can be used for compare function and PWM-waveform generation. There are three continuous modes of operations for each GP timer in up- or up/down-counting operations. Internal or

29、external input clocks with programmable prescaler are used for each GP timer. GP timers also provide the time base for the other event-manager submodules: GP timer 1 for all the compares and PWM</p><p>　　Ful

30、l-compare units</p><p>　　There are three full-compare units on each event manager. These compare units use GP timer1 as the time base and generate six outputs for compare and PWM-waveform generation using pr

31、ogrammable deadband circuit. The state of each of the six outputs is configured independently. The compare registers of the compare units are double-buffered, allowing programmable change of the compare/PWM pulse widths

32、as needed.</p><p>　　Programmable deadband generator</p><p>　　The deadband generator circuit includes three 8-bit counters and an 8-bit compare register. Desired deadband values (from 0 to 24

33、81;s) can be programmed into the compare register for the outputs of the three compare units. The deadband generation can be enabled/disabled for each compare unit output individually. The deadband-generator circuit prod

34、uces two outputs (with or without deadband zone) for each compare unit output signal. The output states of the deadband generator are configurable and c</p><p>　　PWM waveform generation</p><p>　

35、　Up to eight PWM waveforms (outputs) can be generated simultaneously by each event manager: three independent pairs (six outputs) by the three full-compare units with programmable deadbands, and two independent PWMs by

36、the GP-timer compares.</p><p>　　PWM characteristics</p><p>　　Characteristics of the PWMs are as follows:</p><p>　　16-bit registers</p><p>　　Programmable deadband for th

37、e PWM output pairs, from 0 to 24 µs</p><p>　　Minimum deadband width of 50 ns</p><p>　　Change of the PWM carrier frequency for PWM frequency wobbling as needed</p><p>　　Change o

38、f the PWM pulse widths within and after each PWM period as needed</p><p>　　External-maskable power and drive-protection interrupts</p><p>　　Pulse-pattern-generator circuit, for programmable gene

39、ration of asymmetric, symmetric, and four-space vector PWM waveforms</p><p>　　Minimized CPU overhead using auto-reload of the compare and period registers</p><p>　　Capture unit</p><p&

40、gt;　　The capture unit provides a logging function for different events or transitions. The values of the GP timer 2 counter are captured and stored in the two-level-deep FIFO stacks when selected transitions are detected

41、 on capture input pins, CAPx (x = 1, 2, or 3 for EVA; and x = 4, 5, or 6 for EVB). The capture unit consists of three capture circuits.</p><p>　　Capture units include the following features:</p><p

42、>　　One 16-bit capture control register, CAPCON (R/W)</p><p>　　One 16-bit capture FIFO status register, CAPFIFO (eight MSBs are read-only, eight LSBs are write-only)</p><p>　　Selection of GP t

43、imer 2 as the time base</p><p>　　Three 16-bit 2-level-deep FIFO stacks, one for each capture unit</p><p>　　Three Schmitt-triggered capture input pins (CAP1, CAP2, and CAP3)—one input pin per cap

44、ture unit. [All inputs are synchronized with the device (CPU) clock. In order for a transition to be captured, the input must hold at its current level to meet two rising edges of the device clock. The input pins CAP1 an

45、d CAP2 can also be used as QEP inputs to the QEP circuit.]</p><p>　　User-specified transition (rising edge, falling edge, or both edges) detection</p><p>　　Three maskable interrupt flags, one fo

46、r each capture unit</p><p>　　Enhanced analog-to-digital converter (ADC) module</p><p>　　A simplified functional block diagram of the ADC module is shown in Figure 1. The ADC module consists of a

47、 10-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module include:</p><p>　　10-bit ADC core with built-in S/H</p><p>　　Fast conversion time (S/H + Conversion) of 500

48、 ns</p><p>　　16-channel, muxed inputs</p><p>　　Autosequencing capability provides up to 16 “autoconversions” in a single session. Each conversion can be programmed to select any 1 of 16 input ch

49、annels</p><p>　　Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer (i.e., two cascaded 8-state sequencers)</p><p>　　Sixteen result registers (indi

50、vidually addressable) to store conversion values</p><p>　　Multiple triggers as sources for the start-of-conversion (SOC) sequence</p><p>　　S/W – software immediate start</p><p>　　EV

51、A – Event manager A (multiple event sources within EVA)</p><p>　　EVB – Event manager B (multiple event sources within EVB)</p><p>　　Ext – External pin (ADCSOC)</p><p>　　Flexible int

52、errupt control allows interrupt request on every end of sequence (EOS) or every other EOS</p><p>　　Sequencer can operate in “start/stop” mode, allowing multiple “time-sequenced triggers” to synchronize conve

53、rsions</p><p>　　EVA and EVB triggers can operate independently in dual-sequencer mode</p><p>　　Sample-and-hold (S/H) acquisition time window has separate prescale control</p><p>　　B

54、uilt-in calibration mode</p><p>　　Built-in self-test mode</p><p>　　The ADC module in the ’240x has been enhanced to provide flexible interface to event managers A and B. The ADC interface is bui

55、lt around a fast, 10-bit ADC module with total conversion time of 500 ns (S/H + conversion). The ADC module has 16 channels, configurable as two independent 8-channel modules to service event managers A and B. The two in

56、dependent 8-channel modules can be cascaded to form a 16-channel module. Figure 2 shows the block diagram of the ’240x ADC module.</p><p>　　The two 8-channel modules have the capability to autosequence a ser

57、ies of conversions, each module has the choice of selecting any one of the respective eight channels available through an analog mux. In the cascaded mode, the autosequencer functions as a single 16-channel sequencer. On

58、 each sequencer, once the conversion is complete, the selected channel value is stored in its respective RESULT register. Autosequencing allows the system to convert the same channel multiple times, allowing the u</p&

59、gt;<p>　　Figure 2. Block Diagram of the ’240x ADC Module</p><p>　　TMS320LF2407, TMS320LF2406, TMS320LF2402</p><p>　　TMS320LC2406, TMS320LC2404, MS320LC2402</p><p><b>　　

60、數(shù)字信號處理控制器</b></p><p>　　TMS320LF240x和TMS320LC240x系列芯片作為’24x系列DSP控制器的新成員，是C2000平臺下的一種定點DSP芯片?！?40x芯片為以’C2xx為核心CPU的增強型的TMS320結構設計提供了低成本、低功耗、高性能處理能力。芯片集成了用以優(yōu)化電機數(shù)字控制應用的一些高級外設，以實現(xiàn)一個真正的單芯片DSP控制器。與現(xiàn)有的’24x DSP控

61、制芯片編碼兼容的通知，’240x系列芯片具有更好的處理能力（30 MIPS）和更高級的集成外設。</p><p>　　’240x系列芯片提供一系列不同的存儲空間和不同的外設搭配，以滿足各種應用中特殊的性價比要求。高達32K的FLASH存儲空間為以下應用提供了可重復編程的解決方案：</p><p>　　需要整體編程能力升級的應用</p><p>　　移植到基于ROM的

62、設備的應用的開發(fā)和初始化</p><p>　　Flash芯片和對應的ROM芯片引腳是完全逐一兼容的?；趂lash的芯片包含一個256字節(jié)的引導ROM，使在線編程十分便利。</p><p>　　所有的’240x系列芯片至少提供一個用以優(yōu)化數(shù)字控制電機和電源的事件管理模塊。該模塊可以提供中間和/或邊緣排列的PWM發(fā)生器，為防止穿透型擊穿可編程死區(qū)以及同步的A/D轉換器。帶有雙事件管理器的芯片

63、一個DSP芯片就可控制多個電機和/或轉換控制器。</p><p>　　高性能的十位模擬-數(shù)字轉換器（ADC）最低轉換時間是500ns，可以提供多達16通道的模擬輸入。具有自動排序功能的ADC在一個轉換周期內允許最多16次轉換而不增加任何CPU開銷。</p><p>　　芯片內集成了串行通信接口（SCI）以同系統(tǒng)中的其他設備進行異步通信。對于要求額外通信接口的系統(tǒng)，’2407, ’2406

64、和 ’2404芯片提供一個16位的同步串行外設接口（SPI）。’2407 和 ’2406芯片提供控制器局域網通信模塊，符合2.0B規(guī)范的要求。為了最大化設備的易用性，功能引腳也可配置為通用的I/O接口（GPIO）。</p><p>　　為了開發(fā)的流線性，每塊芯片都集成了基于SCAN的JATG適配器，這為數(shù)字控制系統(tǒng)的調試提供了在線實時調試能力。一整套從C編輯器到工業(yè)級的代碼編譯調試器的工具支持這一系列的芯片。很多

65、第三方開發(fā)軟件不僅提供設備級的開發(fā)工具，并且支持系統(tǒng)級的設計和開發(fā)。</p><p><b>　　外設</b></p><p>　　對TMS320x240x系列芯片的集成外設包括：</p><p>　　1.兩個事件管理模塊</p><p>　　2.增強型模擬-數(shù)字轉換（ADC）模塊</p><p>

66、;　　3.控制器局域網（CAN）模塊</p><p>　　4.串行通信接口（SCI）模塊</p><p>　　5.基于鎖相環(huán)的時鐘模塊</p><p>　　6.數(shù)字輸入/輸出以及引腳復用功能</p><p>　　7.外部存儲器接口（僅’LF2407）</p><p>　　8.看門狗（WD）時鐘模塊</p>

67、<p>　　事件管理器模塊（EVA,EVB）</p><p>　　事件管理器模塊包括通用（GP）定時器、全比較/PWM單元、捕捉單元以及正交編碼脈沖（QEP）電路。EVA和EVB的定制器、比較單元以及捕捉單元的功能都是一致的。只是定時器和單元的名稱不同。表1列出了所用的模塊和信號的名稱，列出了事件管理器模塊的可用特征與功能，并著重講解了EVA模塊。</p><p>　　事件管理

68、器A和B擁有相同的外圍寄存器。EVA的起始地址是7400h，EVB的起始地址是7500h。本節(jié)以EVA為例描述了通用（GP）定時器、比較單元、捕捉單元以及正交編碼脈沖（QEP）的功能。EVB模塊也有相同的功能，只是模塊/信號的名稱不同。</p><p>　　表1 EVA與EVB的模塊與信號名稱</p><p><b>　　通用定時器</b></p>&

69、lt;p>　　每個事件管理模塊包含2個通用定時器：定時器x（對EVA，x=1或2；對EVB，x=3或4）包括：</p><p>　　一個16位定時器、增減計數(shù)的計數(shù)器TxCNT，可讀寫</p><p>　　一個16位定時器比較寄存器（雙緩沖，帶影子寄存器）TxCMPR，可讀寫</p><p>　　一個16位定時器比較寄存器（雙緩沖，帶影子寄存器）TxPR，可讀

70、寫</p><p>　　一個16位定時器控制寄存器TxCON，可讀寫</p><p>　　可選擇的內部或外部輸入時鐘</p><p>　　用于內部或外部時鐘輸入的可編程的預定標器</p><p>　　控制和中斷邏輯用于四個可屏蔽中斷：下溢、溢出、定時器比較和周期中斷</p><p>　　一個可選擇方向的輸入引腳(TDI

71、R)（當用雙向計數(shù)方式時用來選擇向上或向下計數(shù)）</p><p>　　每個GP定時器既可以相互獨立運行，又可以同步工作。與GP定時器相關的比較寄存器既可用作比較功能，也可用于PWM波形的發(fā)生。每個GP定時器在加或加減計數(shù)時有三種連續(xù)工作的模式。每個GP定時器都擁有可編程預定標的內部或外部輸入時鐘。GP定時器還向事件管理器的子模塊提供時基。GP定時器1向所有比較單元和PWM電路提供時基。GP定時器2/1還向捕捉單元

72、以及正交脈沖計數(shù)操作提供時基。周期寄存器和比較寄存器的雙緩沖允許根據需要編程修改定時器的周期以及比較/PWM的脈寬。</p><p><b>　　全比較單元</b></p><p>　　每個事件管理器模塊包含三個全比較單元。這些單元以GP定時器1作為時基，可產生六路輸出用于比較和可編程死區(qū)電路的PWM波形。這六個輸出的狀態(tài)可以獨立配置。比較單元的比較寄存器是雙緩沖的，

73、允許依據需要編程控制比較/PWM的脈沖寬度。</p><p><b>　　可編程死區(qū)發(fā)生器</b></p><p>　　死區(qū)發(fā)生器電路包括三個8位計數(shù)器和一個8位比較寄存器，死區(qū)時間間隔（0~24 µs）可根據需要編程存入比較寄存器以控制三個比較單元的輸出。每個比較單元的死區(qū)發(fā)生器可以獨立的使能或取消。死區(qū)產生電路（不論是否有死區(qū)空間）對每一比較單元產生兩路

74、輸出。通過雙緩沖的ACTR寄存器，死區(qū)發(fā)生器的輸出狀態(tài)可根據需要配置或改變。</p><p><b>　　PWM波形發(fā)生器</b></p><p>　　每個事件管理器可以同時產生多達8路的PWM波形（輸出）：有可編程死區(qū)功能的三個全比較單元產生三對（6個輸出）獨立的波形，GP定時器比較產生兩個獨立的PWM波形。</p><p><b>

75、;　　脈寬調制電路</b></p><p>　　脈寬調制電路波形的特征如下：</p><p><b>　　16位寄存器</b></p><p>　　有從0到24µs的可編程死區(qū)發(fā)生器控制每一個輸出對</p><p>　　最小死區(qū)寬度為50ns</p><p>　　依據需要可以

76、改變PWM的載波頻率</p><p>　　在每個PWM周期內或之后可依據需要改變PWM的脈沖寬度</p><p>　　外部可屏蔽的功率驅動保護中斷</p><p>　　脈沖形式發(fā)生器電路，用于可編程的對稱、非對稱以及4個空間矢量PWM波形產生</p><p>　　自動重裝載的比較和周期寄存器使CPU的負擔最小</p><p

77、><b>　　捕捉單元</b></p><p>　　此單元可采集每個事件或跳變。當偵查到輸入引腳CAPx（對EVA，x=1、2或3；對EVB，x=4、5或6）上有與設定想通的跳變時，GP定時器2的計數(shù)值會被存入一個兩級的FIFO棧中。捕捉單元由三個捕捉電路構成。</p><p>　　捕捉單元的特征如下：</p><p>　　一個16位的捕

78、捉控制寄存器CAPCON（可讀寫）</p><p>　　一個16位的捕捉FIFO寄存器CAPFIFO（8位MSBs只讀，8位LSBs只寫）</p><p>　　以通用GP定時器2作為時基</p><p>　　3個16位兩級深的FIFO，每個捕捉單元一個</p><p>　　3個施密特觸發(fā)器（CAP1/2/3），每個捕捉單元一個輸入引腳?！舅?/p>

79、的輸入與內部CPU時鐘同步，為了使跳變被捕獲，輸入必需在當前電平保持兩個CPU時鐘周期。輸入引腳CAP1/2和CAP4/5也可用作正交編碼脈沖電路的正交編碼脈沖輸入】</p><p>　　用戶可定義的跳變檢測方式（上升沿、下降沿或任意跳變）</p><p>　　三個可屏蔽中斷標志位，每個捕捉單元一個</p><p>　　增強型模擬-數(shù)字轉換（ADC）模塊</p

80、><p>　　圖2是ADC模塊的功能框圖。通過一個內置抽樣和保持電路，ADC模塊可進行10位ADC變換。此模塊的功能如下：</p><p>　　帶內置采樣/保持（S/H）的10位模數(shù)轉換模塊ADC</p><p>　　轉換時間快（采樣/保持+轉換），金庸500ns</p><p>　　16個可選擇的模擬輸入通道</p><p&

81、gt;　　自動排序功能。一次可執(zhí)行最多16個通道的“自動轉換”，而且每次要轉換的通道都可通過編程選擇</p><p>　　排序器即可當作兩個八位的排序器，也可用作一個大的16位排序器（例：兩個級聯(lián)的八位排序器）</p><p>　　16個結果寄存器（獨立編址），用以存儲轉換結果</p><p>　　多個觸發(fā)器可以啟動AD轉換：</p><p>

82、;　　S/W - 軟件立即啟動</p><p>　　EVA – 事件管理器A（在事件管理器A中有多個事件源可以啟動AD轉換）</p><p>　　EVB – 事件管理器B（在事件管理器B中有多個事件源可以啟動AD轉換）</p><p>　　外部 – ADCSOC引腳</p><p>　　靈活的中斷控制允許在每一個或每隔一個序列結束時產生中斷請

83、求</p><p>　　排序器可以工作在啟動/停止模式，允許多個按時間排序的觸發(fā)源同步轉換</p><p>　　EVA和EVB各自獨立的觸發(fā)SEQ1和SEQ2(僅在雙排序模式)</p><p>　　采樣和保持獲取時間窗口有獨立的預定標機制</p><p><b>　　內置校驗模式</b></p><p

84、><b>　　內置自測試模式</b></p><p>　　’240x的ADC模塊已經被加強從而為事件管理器提供了靈活的接口。ADC接口圍繞在一個快速的10位ADC模塊旁，總轉換時間為500ns（采樣/保持+轉換）。ADC模塊擁有16個通道，可配置為兩個獨立的8通道模塊以服務于事件管理器A和B。兩個獨立的8通道模塊可級聯(lián)為一個16位的模塊。表2為’240x ADC模塊的功能框圖。<

85、/p><p>　　兩個8通道的模塊也可將輸入自動排序為一系列轉換。通過模擬輸入選擇器，每個模塊可選擇各自輸入的八個通道。在級聯(lián)模式，可形成一個16通道的自動排序器。在每個排序其中，一旦轉換結束，所選擇的通道的轉換值將會被存入對應的結果寄存器。自動排序功能允許系統(tǒng)多次轉換同一通道，允許用戶執(zhí)行過抽樣法則。這可使傳統(tǒng)的信號抽樣轉換結果得以增強。</p><p>　　圖2 ＇240x ADC模塊功