外文翻譯---基于fpga系統(tǒng)的數(shù)字信號(hào)處理適用性評(píng)估

1、1一、英文原文 一、英文原文An Assessment of the Suitability of FPGA-Based Systems for use in Digital Signal Processing★ ★★Russell J. Petersen and Brad L. HutchingsBrigham Young University, Dept. of Electrical and Computer Engineering

2、, 459 CB,Provo UT 84602, USAAbstract. FPGAs have been proposed as high-performance alternatives to DSP processors. This paper quantitatively compares FPGA performance against DSP processors and ASICs using actual applica

3、tions and existing CAD tools and devices. Performance measures were based on actual multiplier performance with FPGAs, DSP processors and ASICs. This study demonstrates that FPGAs can provide an order of magnitude better

4、 performance than DSP processors and can in many cases approach or exceed ASIC levels of performance.1 IntroductionTo meet the intensive computation and I/O demands imposed by DSP systems many custom digital hardware sys

5、tems utilizing ASICs have been designed and built. Custom hardware solutions have been necessary due to the low performance of other approaches such as microprocessor-based systems, but have the disadvantage of inflexibi

6、lity and a high cost of development. The DSP processor attempts to overcome the inflexibility and development costs of custom hardware. The DSP processor provides flexibility through software instruction decoding and exe

7、cution while providing high performance arithmetic components such as fast array multipliers and multiple memory banks to increase data throughput. The FPGA has also recently generated interest for use in implementing di

8、gital signal processing systems due to its ability to implement custom hardware solutions while still maintaining flexibility through device reprogramming [2]. Using the FPGA it is hoped that a significant ★ To be publis

9、hed in 5th International Workshop on Field-Programmable Logic and Applications, Oxford, England, Aug. 1995.★★This work was supported by ARPA/CSTO under contract number DABT63-94-C-0085 under a subcontract to National S

10、emiconductor.3Fig. 1. Block diagrams of basic multiplier alternatives2.2 FPGA multiplication resultsTable 1 lists the performance of several multipliers implemented on three different FPGAs. The FPGAs used were a Xilinx

11、4010, an Altera Flex8000 81188, and a National Semiconductor CLAy31. The first two FPGAs can be characterized as medium-grained architectures and are approximately equivalent in logic-density while the last FPGA is a fin

12、e-grained architecture utilizing smaller but more numerous cells. The multiplication rate of each multiplier is listed in MHz as well as the percentage of the FPGA required to implement the multiplier. The bit-serial mul

13、tipliers have listed both their clock rate (bit-rate) and their effective multiplication rate (clock rate/2N).2.3 Multiplier table contentsThe majority of the multipliers in this study used common architectures such as t

14、he Baugh-Wooley two's complement parallel-array multiplier [5] and pipelined versions of the bit-serial multiplier [6] shown in Figure 1. In addition, several custom parallel multipliers were built that take advantag

15、e of the special features available on the Altera and Xilinx FPGAs. These are intended to represent near the absolute maximum possible multiplier performance that can be achieved with these current FPGAs. These specific

16、customizations will be discussed below.Table 1. FPGA Multiplier Performance ResultsType of Multiplier # CLB/LC's % of FPGA Mult. SpeedAltera 81188 Parallel Multipliers8-bit unsigned fast-adder8-bit signed fast-adder8