低電壓SRAM時(shí)序控制電路技術(shù)研究.pdf

1、獨(dú)創(chuàng)性聲明本人聲明所呈交的學(xué)位論文是本人在導(dǎo)師指導(dǎo)下進(jìn)行的研究工作及取得的研究成果。據(jù)我所知，除了文中特別加以標(biāo)注和致謝的地方外，論文中不包含其他人已經(jīng)發(fā)表或撰寫過的研究成果，也不包含為獲得安徽大學(xué)或其他教育機(jī)構(gòu)的學(xué)位或證書而使用過的材料。與我一同工作的同志對(duì)本研究所做的任何貢獻(xiàn)均已在論文中作了明確的說明并表示謝意。學(xué)位論文作者簽名：a十亞氛簽字日期：知Is年6月1日學(xué)位論文版權(quán)使用授權(quán)書本學(xué)位論文作者完全了解安徽大學(xué)有關(guān)保留、使用學(xué)位

2、論文的規(guī)定，有權(quán)保留并向國家有關(guān)部門或機(jī)構(gòu)送交論文的復(fù)印件和磁盤，允許論文被查閱和借閱。本人授權(quán)安徽大學(xué)可以將學(xué)位論文的全部或部分內(nèi)容編入有關(guān)數(shù)據(jù)庫進(jìn)行檢索，可以采用影印、縮印或掃描等復(fù)制手段保存、匯編學(xué)位論文。(保密的學(xué)位論文在解密后適用本授權(quán)書)學(xué)位論文作者簽名：葉亞泵簽字日期：和哆年6月1日郢繇：兩鋸址簽字日期：9o15年6月1日低!也jliSRAM㈣『事空帝J電路j支術(shù)研究AbstractInrecentyem‘S，themob

3、ileInternettechnologyhasbeendevelopingwithhighspeed，whichleadstoafactthattheneedofStaticRandomAccessMemory(SRAMforshort、formicroprocessorandsystem011chipismoreandmoreimportantWiththefurtherdevelopmentofscalingtechnique，s

4、upplyvoltageofchipisbecominglowerHoweverprocessvariationisalsoincreased，whichwillaffecttheperformanceofsystemForexample，itwillincreasethetimingmarginofSRAMtimingcontrolcircuit，reducetheSRAMspeedandincreasethepowerconsump

5、tionofSRAMInordertosolvethisproblem，timingcontrolcircuitoflowvoltageSRAMisresearchedindepthinthispaperThemainworkofthispaperisasfollows：FirstlythecircuitstructureandworkingprincipleofSRAtVlisintroducedThen，theeffectoftim

6、ingoptimizationbetweeninverterdelaychainandtraditionalreplicabitlinetechniqueiscomparedInaddition，severalnoveltechniquesaboutreplicabit—line，theirprincipleandcircuitstructurearetoldinthispaperwhichareconfigurablereplicab

7、itlinetechnique，multi—stagereplicabit—linetechnique，digitizedreplicabit—linedelaytechniquejmultiple—stageparallelreplicabit—linedelayadditiontechniqueanddualreplicabitlinedelaytechniqueFurthermore，theresultsofMonteCarlos

8、imulationofthesetechniqueswillbecomparedindifferentcomerAtthesametime，theweaknessesofthesetechniqueswillbeanalyzedFinallyanovelreplicabitlinetechniquenamed8transistordualdigitizedreplicabitlinedelaytechniqueisputforwardi

9、nthispaperwhichwillreducetimingvariationofSenseAmplifierEnableSignal(SAEforshort)forStaticRandomAccessMemoryTheproposedtechniquecombinesdigitizedreplicabit—linetdelaytechniqueanddualreplica’bit—linedelaytechnique，whichre

10、ducestheSAEvariationtoaverylowlevelAtthesametime，anovelgtransistorreplicacellisproposedComparedwiththetraditionalreplicabit—linetechnique，whenthesupplyvoltageandtemperaturearerespectively07Vand125degreeCelsius，theSAEvari