hardware software co-design a case study of next generation single chip pda

1、Hardware/Software Co-Design:A Case Study of Next Generation Single Chip PDA,R. C. ChangDepartment of Computer and Information ScienceNational Chiao Tung University,Outline,IntroductionCadence Virtual Component Co-Des

2、ignSingle Chip PDA ModelingHardware/Software Trade-OffsConclusion,Design Space Exploration,© CadenceTM,Hardware/Software Representations,Various models contain strong properties that might be useful for some appl

3、icationsPropertiesTiming, Clock Mechanism, Communication Method, Hierarchy, Determinism, Math FormalismComputation Model: Finite State Machine, Discrete Event System, Communicating Processes, Petri Nets, Synchronous/

4、Reactive Models, Control/Dataflow Graphics,Cierto Virtual Component Co-Design,Tool from Cadence Design SystemBased on POLIS Project of UCB EECSUse Codesign Finite State Machine representation modelA front-end for SoC

5、design flow,Virtual Component Co-Design,Benefit from IPs reuseSystem Level IPs IntegrationExplore partitioning trade-offs before synthesisSeparate a system into Behavior (function, application) and Architecture Separ

6、ate a model into function and performance,Conventional HW/SW Co-Design,,,,VCC Design Flow,Wireless Multimedia PDA,,,,,,,,Base Station,Wire,Wireless,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,PC,PDA,PDA Modeling,Heavy Application (Fu

7、nction, Behavior)Video playback: MPEG4 VideoVideo Phone: H.324/M (Video -- H.263)ArchitectureSingle ChipProcessor, DSP (optional)Bus, BridgeRAM, Flash, Peripheral,H.263 Codec Block Diagram,H.263 Behavior Diagram,,

8、Bitstream,Packet,Packet,Bitstream,YUV,RGB,10 Hz,YUV,,,Functional Simulation Model,,Model Definition,Input ports,Output ports,Parameters,Implementation,Create VCC Types (ports, parameters)YUVFrame、RGBFrame、PacketCreate

9、 Encoder & Decoder BlocksCreate Whitebox C model from C projectTMN-2.0 (H.263 ver.1 baseline codec)Interact with external via port manipulationEmbedded Waits API,Implementation (cont.),Create Packetizer & De-

10、PacketizerConvert between Bitstream and PacketCreate Sensor, Display, Net BlocksConnect simulation to Win32 environmentSensor: Read YUV Frames from fileDisplay: Display Frame with Win32 GDINet: Buffer Packet and si

11、mulate network,Performance Model,,i,B,i,o,p,o,p,,,,Functional model,Performance model,,Input delay,Output delay,,,PDA Architecture,,Peripheral Bus,Architecture Diagram,,,Processor,Modified from ARM7TDMI modelARM922T: AR

12、M9TDMI + 8K I-Cache + 8K D-Cache + MMUCache: 8Kbytes, 256 lines of 32 bytes, 64 way set-associative.,RTLinux,Interrupt Latency< 10 us for embedded processor (RTLinux)Scheduling Latency4 ms (RTSS2000)2-6 ms (Maili

13、ng List),Hardware/Software Partitioning,Map to RTOSSoftwareMap to ASICHardwareHexagramCommunication Pattern,ARM9 Core,Software with microprocessorImpossible to encode video in realtimeAthlon 500, FreeBSD 4.3R,

14、 GCC 2.95.3, 341 frames dataOptimized with -O2: 49.92secNon-Optimized: 110.48sec,ARM9 + DSP Extension,ARM922T + TI TMS320C6200Manual Annotated Performance ModelEncoder ProfileSAD Optimization,ARM9 + ASIC codec,ASIC

15、 performance model can only be created manuallyASIC development is not an issue of VCCIf our system contains a H.263 codec ASIC, the performance of our case is determined by ASIC performance,Simulation Result (Decoder)

16、,ARM9 only17 MHz,ARM9 + DSP14 MHz,Simulation Result (Encoder),ARM + DSP180 MHz,,Simulation Result (Full Codec),ARM + DSP195 MHz,,Conclusion,Convert a existing C Project to VCC behavior modelCreate PDA model and a H.

17、263 full-duplex codec in VCC environmentRun performance simulations to determine the CPU clock rate,True Value of VCC,IP reuseRapid system prototyping & production versioningSystem level design space exploringTes