電氣電子專業(yè)畢業(yè)設(shè)計(jì)外文翻譯--用spmc75的pdc定時(shí)器做bldc電機(jī)的速度檢測(cè)

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1、　　XXXX大學(xué)　?。ㄍ馕姆g材料）　　學(xué)院：　　專業(yè)：　　學(xué)生姓名：</b&

2、gt;　　指導(dǎo)教師：　　BLDC Motor Speed Estimation Using PDC Timer Module　　1 Speed Calculation of BLDC 　　1.1 Summary of BLDC<

3、/p>　　Since current BLDC has substituted the electrical commutator for the mechanical one, it eliminates the disadvantages of noise, spark, electromagnetic disturbance, short lifetime, etc. Now BLDC is provi

4、ded with advantages of simple structure, dependable operation and easy maintenance as AC motor does, as well as advantages of high efficient, no excitation cost and functional speed regulation as traditional DC motor doe

5、s. So it is widely used in various fields of industrial control now.　　1.2 PDC Module Introduction 　　SPMC75F2413A provides two channels of 16 bit PDC (Phase Detection Control, PDC

6、) timers used for capture function and PWM operation. It also supports position detection features for Brushless-DC motor application. The PDC timers are very suitable for both mechanical speed calculation, with ACI and

7、BLDC motor included, and phase commutation for changing current conduction according to position information. Figure 1-1 shows the block diagram of entire PDC timers, channel 0 and channel 1. For detail<p&

8、gt;　　Table 1-1 PDC Timer　　Figure 1-1 PDC Timers Block Diagram 　　1.3 PDC Operation 　　This note mainly depicts PDC application in motor speed measurement. For

9、detailed PDC introduction, please refer to “SPMC75F2413A Programming Guide” authored by Sunplus. 　　PDC module has four types of registers to perform speed measurement: Timer control register P_TMRx_C

10、trl (x = 0, 1), position detection control register P_POSx_DectCtrl (x = 0, 1), input output control register P_TMRx_IOCtrl (x = 0, 1), and timer interrupt enable register P_TMRx_INT (x = 0, 1). Where, P_TMRx_Ctrl and P_

11、POSx_DectCtrl are introduced in detail. 　　1.31Input Output Control Register 　　P_TMRx_Ctrl(x = 0, 1)　　Bit 15:14 　　SPCK: Capture input sam

12、ple clock select. These bits select the capture input sample clock. Capture input will be sampled with sample clock. Pulses shorter than four sample clocks will be considered invalid, and will be ignored.<

13、p>　　00 = FCK/1 　　01 = FCK/2　　10 = FCK/4 　　11 = FCK/8　　Bit 13:10 　　MODE: Modes select. These bits are used to sel

14、ect the timer operation modes. 　　0000 = Normal operation (continuous counter up counting) 　　0100 = Phase counting mode 1 　　0101 = Phase counting mode 2 </

15、p>　　0110 = Phase counting mode 3 　　0111 = Phase counting mode 4 　　1x0x = Edge-aligned PWM mode (continuous counter up counting, PWM output) 　　1

16、x1x = Center-aligned PWM mode (continuous counter up/down counting, PWM output)　　Bit 9:8 　　CLEGS: Counter clear edge select. These bits select the counter clea

17、ring edge when the clearing source is in input capture mode.　　00 = do not clear 　　01 = rising edge 　　10 = falling edge 　　11 = both edge&

18、lt;/p>　　Bit 7:5 　　CCLS: Counter clear source select. These bits select the TCNT counter clearing source. 　　000 = TCNT clearing disabled

19、;　　001 = TCNT cleared by P_TMRx_TGRA (x = 0, 1) capture input 　　010 = TCNT cleared by P_TMRx_TGRB (x = 0, 1) capture input 　　011 = TCNT cleared by P_TMRx_TGRC (x = 0,

20、1) capture input 　　100 = TCNT cleared by every P_POSx_DectData (x = 0, 1) change 6 times　　101 = TCNT cleared by every P_POSx_DectData (x = 0, 1) change 3 times <p&

21、gt;　　110 = TCNT cleared by P_POSx_DectData (x = 0, 1) position detection data change 　　111 = TCNT cleared by P_TMRx_TPR (x = 0, 1) compare match　　Bit 4:3 <

22、/p>　　CKEGS: Clock edge select, These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved. When FCK/1 is selected as counter clock, counter wi

23、ll count at rising edge if count at both edges is selected.　　00 = Count at rising edge 　　01 = Count at falling edge 　　1X = Count at both edges<

24、;p>　　Bit 2:0 　　TMRPS: Timer pre-scalar select. These bits select the TCNT counter clock source. It can be selected independently for each channel.　　000 = Counts on FCK /1 &

25、lt;/p>　　001 = Counts on FCK /4 　　010 = Counts on FCK /16 　　011 = Counts on FCK /64 　　100 = Counts on FCK /256 　　101 = Coun

26、ts on FCK /1024 　　110 = Counts on TCLKA pin input 　　111 = Counts on TCLKB pin input　　Control register configuration 　　P_TMRx_Ctrl(x = 0,

27、 1) is used for the selection of input capture during speed measurement. Rather than being a general input signal, the input capture is a period between two position detection changes triggered by PDC interrupt. This per

28、iod must be counted with a certain frequency supported by a clock source. Thus, the counters on this function must be configured. 　　MODE: Select a timer operation mode in seven modes. However, only t

29、he normal operation (continuous counter up counting) mode can be selected in this application, because the other six modes are all related to phase counting mode or PWM mode. 　　CCLS: Select a TCNT co

30、unter clearing source from eight settings. In this application, one among the three can be set: 100, 101 or 110, which respectively indicates that TCNT is cleared for once every 6/3/1 times P_the POSx_DectData (x = 0, 1)

31、 changes. Also, they can be described as: TCNT is cleared for once every 360/180/60 electrical degree rotation of BLDC. This setting is critical for converting electrical revolution to mechanical revolution and measuring

32、 the BLDC speed.　　CKEGS: Select the input clock edge, which can be rising, falling or both edges. When the input clock is counted using both edges, the input clock period is halved. Note to count thi

33、s factor on during the BLDC speed calculation. 　　TMRPS: Select the TCNT counter clock source from eight settings. This setting determines the precision and the range during BLDC speed measurement. Se

34、e the example code below: 　　P_TMR0_Ctrl, B.MODE = 0; // Normal Counting mode 　　P_TMR0_Ctrl, B.CCLS = 6; // TCNT cleared by P_POSx_DectData (x = 0, 1)

35、　　// Each time position detection data change 　　P_TMR0_Ctrl, B.CKEGS = 0; // Counting at rising edge 　　P_TMR0_Ctrl, B.TMRPS = 3;

36、 // Select FCK/64 clock source 　　1.3.2 Position Detection Control Register 　　P_POSx_DectCtrl(x = 0, 1) 　　Bit 15:14 　　SPLCK

37、: Sampling clock select. Select FCK/4, FCK/8, FCK/32, or FCK/128 for position sampling clock 　　00 = FCK/4 　　01 = FCK/8 　　10 = FCK/32 　　1

38、1 = FCK/128　　Bit 13:12　　SPLMOD: Sampling mode select. Select one of three modes: sampling when PWM signal is active (PWM is on), sampling regularly, or samplin

39、g when lower side (UN, VN, WN) phases are conducting current. 　　00 = Sample when UPWM/VPWM/WPWM bit is set in P_TMRx_OutputCtrl (x = 3, 4) register and generate the PWM waveform

40、　01 = Sample regularly 　　10 = Sample when lower phases is in active state and conducting current 　　11 = Reserved　　Bit 11:8<

41、p>　　SPLCNT: Sampling count select. These bits select the sampling count for the valid external position detection signals. The position signals must be sampled continuously match as many times as the sampling count se

42、t, for the position signals to be considered valid. The valid settings are from 1 to 15 times. Note that count 0 and 1 are assumed to be one time.　　Bit : 7　　PD

43、EN: Position detection enable. This bit enables/disables the position detection function for position input pins TIOA~C. When enabled, the input signals of these pins will be sampled and the results will be latched to PD

44、R [2:0] bits in POS_DectData register. When disabled, PDR [2:0] will remain its status. 　　0 = Disable 　　1 = Enable　　Bit 6:0<

45、;p>　　SPDLY: Sampling delay. These bits set a delay time clock in which at SPLCK clock source. It is used to stop sampling in order to prevent erroneous detection due to noise that occurs immediately after PWM output t

46、urns on.　　Position detection control register 　　When the position detection changing event occurs, the P_TMRx_TCNT (x = 0, 1) value can be transferred to TGRA. If the position de

47、tection interrupt enable bit PDCIE is set to 1 in the corresponding P_TMRx_INT (x = 0, 1) register, the PDC interrupt routine will be called to process the data. 　　SPLCK: Select sampling clock from F

48、CK/4, FCK/8, FCK/32, or FCK/128 for position sampling clock, which determines the detection precision of position change. Proper setting of SPLCK, SPLCNT and SPDLY will help to prevent erroneous detection and filter the

49、disturbance. 　　SPLMOD: Select one of these three modes: sampling when PWM signal is active (PWM is on), sampling regularly, or sampling when lower side (UN, VN, WN) phases are conducting current. <

50、;/p>　　SPLCNT: Sampling count select. The valid settings are from 1 to 15 times. Note that count 0 and 1 are both assumed to be one time. 　　PDEN: This bit enables/disables the position d

51、etection function for position input pins TIOA~C. 　　SPDLY: Sampling delay with the range of 0 to 127.　　The setting example is shown as blew. 　　P_POS0_DectCtr

52、l, B.SPLCK = 2; // Count on FCK/32 　　P_POS0_DectCtrl, B.SPLMOD = 1; // Sample regularly 　　P_POS0_DectCtrl, B.SPLCNT = 10;

53、 // Sample 10 times 　　P_POS0_DectCtrl, B.PDEN = 1; // Enable position detection　　P_POS0_DectCtrl, B.SPDLY = 100; // Sample Delay

54、　　1.4 Speed Calculation　　In order to obtain the exact parameters, the data must be filtered after captured. There are many filter algorithms, such as low-pass filter, moving average filter,

55、 median filter, average filter, limiting filtering, first-order filter, moving average filtering, etc. In general, the data can be considered valid after processed by these filters. Then the speed can be calculated by su

56、bstituting these parameters data in the formula. 　　Assume Fcap is PDC capture clock frequency; p is the pole-pair of BLDC rotor; TCNT is cleared every m P_POSx_DectData (x = 0, 1) changes, that is, T

57、CNT is cleared at every rad rotation (m=1, 3, 6), and the position data is Ncap　　Since: (Formula 1- 1)　　and =, <

58、/p>　　Since electrical degree = p x mechanical rotation then the mechanical angular 　　velocity is (Formula 1- 2)　　with the u

59、nit of rad/min. Take n as the indicator. 　　So: rad/min (Formula 1- 3) 　　n summarize: rpm (Formula 1- 4) 　　From t

60、he formula above, we can obverse that n is related to Fcap, m, Ncap and p (that is a constant when BLDC is selected) .　　Suppose there is a BLDC with 2 pole-pair, 4000rpm rated speed. We will show you

61、 how to set the parameters of Fcap and m. 　　When m= 1, TCNT is cleared every time P_POSx_DectData (x = 0, 1) changes, , that is, TCNT is cleared for once every 60 electrical degree rotation of BLDC.

62、　　With a certain clock frequency, the motor rotation speed can be calculated by the Formula 1- 4 at the highest speed when Ncap is 1 and the lowest speed when Ncap is 0xffff. 　　T

63、able 1-2 Motor Speed VS Clock Frequency　?。繵hen m= 3, TCNT is cleared for once every 3 times P_POSx_DectData (x = 0, 1) changes, that is, TCNT is cleared every 180 electrical degree rotation of BLDC.

64、　　From the Formula 1- 4, we can see that the measurable motor speed when m= 3 is three times higher than that when m= 1, provided that other parameters are the same. 　?。繵hen m= 6

65、, TCNT is cleared every 6 times P_POSx_DectData (x = 0, 1) changes, that is, TCNT is cleared every 360 electrical degree rotation of BLDC.　　From the Formula 1- 4, we can see that the measurable motor

66、 speed when m= 6 is six times higher than that when m= 1, provides that other parameters are the same. 　　Above all, it is better to set m= 1 to ensure the veracity of positions. Since the highest spe

67、ed can be applied, it is important to select the lowest speed. Assume the lowest measure speed is 200 rpm, we can set Fcap as FCK/16, FCK/64, FCK/256 or FCK/1024. FCK/16 is recommended to be selected for higher veracity.

68、　　1.5 Noise Immunity 　　Through programming the bit value of SPLCNT (sampling count select) and SPDLY (sampling delay) in P_POSx_DectCtrl(x = 0, 1), users could avoid the erroneou

69、s detection due to noise that occurs immediately after PWM output turns on. It can ensure the correctness of speed measurement and phase commutation in BLDC . 　　The valid settings are from 1 to 15 ti

70、mes. Note that count 0 and 1 are both assumed to be one time. These bits select the sampling count for the valid external position detection signals. The position signals must be sampled continuously match as many times

71、as the sampling count set, for the position signals to be considered valid. Then the sharp pulse can be filtered by this method. SPLCK selects the sampling clock. Figure 1-2 shows the sampling counting and Figure 1-3 sho

72、ws the noise immunity 　　Figure 1-2 Sampling Counting 　　Figure 1-3 Noise Immunity Pulse 　　See Figure 1-2 , the SPLCNT setting is 10. When sampling the positio

73、n signal with the frequency that SPLCK selected, a high-to-low transition occurs in hall3 at 0 to1 counting. Then sample the hall signal for ten executive times. If they are all of the same value, the hall signal can be

74、considered valid. 　　When SPLCNT setting is 10, a high-to-low transition occurs in hall3 at the first counting, while a low-to-high transition occurs at the fourth counting. Then reset the counter, sa

75、mple hall3 for ten executive times. If they are all of the same value, the position signals can be considered as 011b still. By this way, a sharp pulse occurring in the signals can be filtered, which prevents the positio

76、n signals from being disturbed. So the position signal will not be sampled if it varies quicker than 　　2 Software Design 　　2.1 Software Description 　　This ap

77、plication note is designed for motor speed measurement when driving BLDC, which is performed by PDC position detection change interrupt. 　　2.2 Source File 　　2.3 DMC Interface<

78、/p>　　Speed1_Now: Current speed by calculation 　　User_R0: PDC Data captured by PDC interrupt 　　2.4 Subroutines 　　3 Design Tips <

79、;p>　　3.1 Demo Listing 　　/*= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = */ 　　// Example 　　/*= = = = = = = = = = = = = =

80、= = = = = = = = = = = = = = = = = = = = = = = = = = */ 　　#include "Spmc75_regs.h" 　　#include "Spmc_typedef.h" 　　#include "unspmacro.

81、h" 　　#include "Spmc75_SPDET.h" 　　main() 　　{ 　　Spmc75_System_Init(); //System initia

82、lization 　　while(1) 　　{ 　　MC75_DMC_UART_Service(); //DMC service 　　}

83、　　} 　　//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =　　// Description: IRQ1 interrupt source is XXX, used to X

84、XX 　　// Notes: Speed measurement through PDC 　　//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 　　void IRQ1(void)__att

85、ribute__((ISR)); 　　void IRQ1(void) 　　{ 　　if(P_TMR0_Status, B.PDCIF && P_TMR0_INT, B.PDCIE) 　　{ </

86、b>　　Spmc75_PDCETSPD_ISR(); // PDC capture interrupt for the motor speed calculation. 　　} 　　}

87、//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 　　// Description: IRQ6 interrupt source is XXX, used to XXX 　　// Notes: DMC receiving ISR &l

88、t;/p>　　//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 　　void IRQ6(void) __attribute__ ((ISR)); 　　void IRQ6(void)

89、　　{ 　　if(P_INT_Status, B.UARTIF) 　　{ 　　if(P_UART_Status, B.RXIF) MC75_DMC_RcvStream(); &l

90、t;b>　　} 　　} 　　Sub-function for speed measurement 　　#define TMRPSFCK (24.0E+6)/64 //Counter clock source

91、　　#define PAIRPOLE 2 //BLDC pole pairs 　　#define PDCCLEAR 1 //CNT clear source 　　#define SPDLIMIT 5000 //Define the highest motor speed to avoid the disturbance due to sharp puls

92、e 　　#define RADIX (UInt32)((TMRPSFCK*60*PDCCLEAR) //(6*PAIRPOLE)) 　　#define MAXRPM (UInt16)(RADIX/SPDLIMIT) 　　static UInt16 a Filter[CAPBSIZE]; //Moving aver

93、age filter data 　　static UInt16 *ptr = a Filter; //Pointer to array 　　void Spmc75_PDCETSPD_ISR(void) 　　{ 　　static UIn

94、t32 summation= 0; 　　UInt16 original, uiSpeed; 　　P_TMR0_Status, B.PDCIF = 1; // Clear interrupt flag 　　original = P_TMR0_TGRA, W;

95、 //Read PDC captured data 　　//Limit the highest speed 　　if(original > P_TMR0_TCNT, W && original > MAXRPM) 　　{

96、　　//Accumulate the captured data and perform moving filter 　　summation -= *ptr; 　　*ptr = original; 　　summation += *ptr; 　　//L

97、oop the array 　　if((++ptr) > (a Filter+CAPBSIZE-1)) ptr = a Filter;　　// Average the accumulation data 　　original = (UInt16)(summation >> SHIFTDIV);

98、　　uiSpeed = (UInt32)RADIX/original; 　　//Speed calculation 　　SPMC_DMC_Save_Aux(0, original); 　　//Transmit captured data to DMC

99、　　SPMC_DMC_Save_SpdNow(1, uiSpeed); 　　//Send data to DMC 　　} 　　} 　　3.2 Main Process Des

100、cription 　　The main program performs system initialization and DMC data detection. While the DMC data detection can also be performed in a timer interrupt with a certain frequency. Figure 3-1 shows t

101、he coding flow. 　　Figure 3-1 Main Process 　　3.3 ISR Description　　In PDC interrupt, system reads and filters the data, then calculates the motor speed. The co

102、ding flow is shown as Figure 3-2 . 　　Figure 3-2 ISR Process 　　3.4Testing Hardware 　　This example is designed for the purpose of study and reference, so we si

103、mply need to input a position signal to test the system. The hardware connection is shown as Figure 3-3 . 　　Figure 3-3 Test Hardware Connection 　　Where, the position signal can b

104、e generated by MCU or special timing logic circuit instead of necessarily being the real signal from BLDC (see Figure 3-4 and Figure 3-5 ). The frequency of position detection change can be adjusted by the potentiometer

105、or ADC in MCU system 　　Figure 3-4 Hall Signal 　　Figure 3-4 shows the three position signals timing with the sequence of 010b, 011b, 001b, 101b, 100b, 110b.

106、　Figure 3-5 Hall signal 　　Figure 3-5 shows Hall3, Hall2, Hall1 timing with the sequence of 110b, 100b, 101b, 001b, 011b, 010b. It is the same to test in real BLDC. The two timings present the differe

107、nt motor directions: move forward or move backward. 　　The Hall.spj file in Appendix shows the code for simulating hall signal with SPMC75F2413A. We can use ADC0 voltage to simulate the speed variatio

108、n, where IOD15, IOD14 and IOD13 are corresponding to Hall3, Hall2 and Hall1 respectively and IOA0/AN0 is used for ADC conversion to adjust the simulated speed. 　　用SPMC75的PDC定時(shí)器做BLDC電機(jī)的速度檢測(cè)

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