ps2鼠標鍵盤協(xié)議 外文翻譯

1、<p>　　畢業(yè)設計(論文)外文資料翻譯</p><p>　　學 院： 信息工程學院 </p><p>　　專 業(yè)： 通信工程092 </p><p>　　姓 名： 趙宏志 </p>

2、<p>　　學 號： 0906220242 </p><p>　　外文出處： www.computer-engineering.org </p><p>　　附 件： 1.外文資料翻譯譯文；2.外文原文。 </p><p>　　附件1：外文資料翻譯譯文&

3、lt;/p><p>　　PS2鼠標鍵盤協(xié)議 </p><p>　　摘要：PS/2接口總線只使用數(shù)據線和時鐘線兩條導線來實現(xiàn)主機與設備的通訊，采用集電極開路實現(xiàn)了一種雙向同步串行協(xié)議。在總線空閑時，兩條線都是高電平。在這種狀態(tài)下，設備才允許開始傳輸數(shù)據。主機對總線有最高的控制權，在任何時候通過將時鐘線拉低就可以禁止設備通信。</p><p>　　關鍵詞：PS/2接口；數(shù)

4、據線；時鐘線；雙向同步串行協(xié)議</p><p><b>　　通訊：概述</b></p><p>　　PS / 2鼠標和鍵盤實現(xiàn)雙向同步串行協(xié)議。該總線是“空閑”時，兩條線都高（集電極開路）。這是唯一的狀態(tài)下，鍵盤/鼠標開始傳輸數(shù)據。主機總線擁有最終控制權，并可能抑制隨時溝通拉時鐘線低。該設備總是產生時鐘信號。如果主機要發(fā)送數(shù)據時，它必須先抑制通信設備拉動時鐘低。主機然

5、后再換低和釋放時鐘數(shù)據。這是“請求發(fā)送”狀態(tài)和信號設備開始產生時鐘脈沖。</p><p>　　摘要：公交數(shù)據=高，時鐘=高： 空閑狀態(tài)。數(shù)據=高，時鐘=低： 通信抑制。數(shù)據=低，時鐘=高： 主機請求到發(fā)送</p><p>　　所有的數(shù)據都發(fā)送一個字節(jié)的時間的11-12位構成一幀中發(fā)送的每個字節(jié)。這些位是：</p><p>　　1個起始位。始終為0。

6、</p><p>　　8個數(shù)據位，至少顯著位第一。</p><p>　　1個校驗位（奇校驗）。</p><p>　　1個停止位。這始終是1。</p><p>　　1，應答位（僅主機到設備通信）</p><p>　　被設置，如果有偶數(shù)個1的數(shù)據位和復位（0），如果有一個數(shù)據位中的1的奇數(shù)奇偶校驗位。數(shù)1的數(shù)據位加上校驗位

7、總是加起來奇數(shù)（奇校驗），這是用于錯誤檢測。鍵盤/鼠標必須檢查此位如果不正確的話，它應該作出反應，如果它已收到一個無效的命令。讀取從設備發(fā)送到主機的數(shù)據在時鐘信號的下降 邊緣上，從主機到設備發(fā)送的數(shù)據的上升沿讀取 時鐘的頻率必須在范圍10 - 16.7千赫。這意味著時鐘要高30 - 50微秒低30 - 50微秒..如果你設計一個鍵盤，鼠標，或主機的模擬器，你應該修改/采樣數(shù)據線在中間的每一個細胞。即15 - 25微秒后相應的時鐘過渡

8、。同樣，鍵盤/鼠標總是產生時鐘信號，但主機總是有通信的最終控制權。定時是絕對至關重要的。在這篇文章中我給每一個時間量必須嚴格遵守。</p><p>　　2.通訊：設備到主機 數(shù)據和時鐘線都是集電極開路。和+5 V的每一行之間的一個電阻連接，所以在總線的空閑狀態(tài)是高的。當鍵盤或鼠標要發(fā)送信息，它首先檢查時鐘線，以確保它是在一個較高的邏輯電平。如果不是的話，主機是抑制通信和設備必須緩沖任何將要發(fā)送的數(shù)據，直

9、到主機釋放時鐘。時鐘線必須持續(xù)至少50微秒之前的設備就可以開始傳輸數(shù)據。 </p><p>　　正如我在上一節(jié)中提到，鍵盤和鼠標使用一個串行協(xié)議與11位幀。這些位是：</p><p>　　1個起始位。始終為0。</p><p>　　8個數(shù)據位，至少顯著位第一。</p><p>　　1個校驗位（奇校驗）。</p><p>

10、;　　1個停止位。這始終是1。</p><p>　　鍵盤/鼠標寫入的數(shù)據線位鐘為高時，由主機時鐘是低時，它是只讀的。圖2和圖3示出了這一點。</p><p>　　圖2：設備到主機的通信。數(shù)據線改變狀態(tài)時，鐘為高時，時鐘是低，數(shù)據是有效的。 </p><p>　　圖3：“Q”鍵（15H）從鍵盤發(fā)送到計算機的掃描碼。通道A是時鐘信號通道B的數(shù)據信號。</p>

11、<p>　　--- 的時鐘頻率為10-16.7千赫。從一個時鐘脈沖的上升沿到數(shù)據轉換的時間必須是至少為5微秒。從數(shù)據轉換到一個時鐘脈沖的下降沿的時間必須是至少5微秒和不大于25微秒。主機可能抑制拉動低時鐘線至少100微秒隨時溝通。如果傳輸被禁止前11個時鐘脈沖，該設備必須中止當前的傳輸和準備數(shù)據重傳的“塊”，當主機釋放時鐘。一個“塊”的數(shù)據可能是一個品牌代碼，斷碼，設備ID，鼠標運動包等，例如，如果鍵盤被中斷，同時發(fā)送兩

12、個字節(jié)的斷碼的第二個字節(jié)，就需要重傳兩個字節(jié)，斷碼，而不僅僅是一個被打斷。如果主機拉時鐘低之前，先高到低時鐘過渡，或者最后一個時鐘脈沖的下降沿后，鍵盤/鼠標不需要重新傳輸任何數(shù)據。但是，如果新的數(shù)據被創(chuàng)建的，需要進行傳輸時，它會被緩沖，直到主機發(fā)行時鐘。鍵盤有一個16字節(jié)的緩沖區(qū)用于此目的。如果發(fā)生價值超過16字節(jié)的按鍵，進一步擊鍵將被忽略，直到緩沖區(qū)中有足夠的空間。小鼠只存儲最新的移動數(shù)據包傳輸。</p><p&

13、gt;　　主機到設備的通訊 主機到設備通信數(shù)據包被發(fā)送一點點不同......</p><p>　　首先，PS / 2設備總是產生時鐘信號。如果主機要發(fā)送數(shù)據時，它必須首先把時鐘和數(shù)據線“請求發(fā)送”狀態(tài)如下：</p><p>　　禁止通信拉動時鐘低至少100微秒。</p><p>　　應用“請求發(fā)送”拉動數(shù)據低，然后釋放時鐘。</p><

14、p>　　設備應該檢查此狀態(tài)下，間隔不超過10毫秒。當設備檢測到這種狀態(tài)下，它會開始產生時鐘信號和時鐘在8個數(shù)據位和1個停止位。主機改變了數(shù)據線，僅當在時鐘線為低電平時，數(shù)據被讀時鐘為高時，由設備。這是相反的什么occours設備到主機的通信。</p><p>　　收到停止位后，設備將承認接收到的字節(jié)，使數(shù)據線低，產生最后一個時鐘脈沖。如果主機不釋放數(shù)據線后的第11個時鐘脈沖，該設備將繼續(xù)產生時鐘脈沖直到數(shù)據

15、線被釋放（然后設備將產生一個錯誤。）</p><p>　　主機可能中止傳輸時前11個時鐘脈沖應答位時鐘線至少100微秒。</p><p>　　為了使這個過程變得更容易理解，這里的主機必須遵循的步驟將數(shù)據發(fā)送到一個PS / 2設備：</p><p>　　1）把時鐘線至少100微秒 2）把數(shù)據線低。3）釋放時鐘線。4）等待設備把時鐘線拉低 5）設置/復位數(shù)據線發(fā)

16、送第一個數(shù)據位 6）等待設備把時鐘拉高7）等待設備把時鐘拉低8）重復步驟5-7，其他7個數(shù)據位，校驗位9）釋放數(shù)據線10）等待設備把數(shù)據線拉低11）等待設備把時鐘線拉低12）等待設備釋放數(shù)據線和時鐘</p><p>　　圖3用圖形表示，圖4的定時顯示由主機產生的信號，而生成的PS / 2設備分開。注意時機“確認”位 - 數(shù)據改變發(fā)生時，時鐘線為高（而不是當它是低，是其它11位的情況下的變化。）<

17、;/p><p>　　圖3：主機到設備的通訊。 </p><p>　　圖4：詳細的主機到設備通信。 </p><p>　　參考圖4，有兩個時間數(shù)量的主機看起來。（a）是所花費的時間的移動設備以開始產生時鐘脈沖后，主機最初需要的時鐘線為低，它必須是不大于15毫秒。（b）是所花費的時間的數(shù)據包要發(fā)送，它必須是不大于2毫秒。如果不符合這些時間限制，主機應產生一個錯誤。

18、立即收到“確認”后，主機可能會帶來抑制通信，數(shù)據處理，而它的時鐘線低。如果由主機發(fā)送的命令，需要一個響應，該響應必須不遲于20毫秒接收主機后釋放時鐘線。如果不會發(fā)生這種情況時，主機將生成一個錯誤。</p><p>　　附件2：外文原文（復印件）</p><p>　　PS2 mouse and keyboard Agreement</p><p>　　Abstract

19、: PS / 2 interface bus using only two wires of the data and clock lines to host communication with the device, the use of open-collector to achieve a two-way synchronous serial protocol. The two lines are high when the b

20、us is idle. In this state, the device is only allowed to begin transmission of data. The highest level of control over the host bus, device communication can be disabled at any time by the clock line low.</p><

21、p>　　Keywords: PS / 2 interface; cable; clock line; bidirectional synchronous serial protocol</p><p>　　Communication: General Description</p><p>　　The PS/2 mouse and keyboard implement a bidir

22、ectional synchronous serial protocol. The bus is "idle" when both lines are high (open-collector). This is the only state where the keyboard/mouse is allowed begin transmitting data. The host has ultimate co

23、ntrol over the bus and may inhibit communication at any time by pulling the Clock line low. </p><p>　　The device always generates the clock signal. If the host wants to send data, it must first inhibit com

24、munication from the device by pulling Clock low. The host then pulls Data low and releases Clock. This is the "Request-to-Send" state and signals the device to start generating clock pulses.</p><p&

25、gt;　　Summary: Bus StatesData = high, Clock = high: Idle state.Data = high, Clock = low: Communication Inhibited.Data = low, Clock = high: Host Request-to-Send</p><p>　　All data is transmitted one byte

26、at a time and each byte is sent in a frame consisting of 11-12 bits. These bits are:1 start bit. This is always 0.</p><p>　　8 data bits, least significant bit first.</p><p>　　1 parity bit (odd

27、 parity).</p><p>　　1 stop bit. This is always 1.</p><p>　　1 acknowledge bit (host-to-device communication only)</p><p>　　The parity bit is set if there is an even number of 1's

28、 in the data bits and reset (0) if there is an odd number of 1's in the data bits. The number of 1's in the data bits plus the parity bit always add up to an odd number (odd parity.) This is used for error dete

29、ction. The keyboard/mouse must check this bit and if incorrect it should respond as if it had received an invalid command.Data sent from the device to the host is read on the falling edge of the clock signal; data sent

30、 from the hos</p><p>　　Timing is absolutely crucial. Every time quantity I give in this article must be followed exactly.Communication: Device-to-Host</p><p>　　The Data and Clock lines are bot

31、h open collector. A resistor is connected between each line and +5V, so the idle state of the bus is high. When the keyboard or mouse wants to send information, it first checks the Clock line to make sure it's at a

32、high logic level. If it's not, the host is inhibiting communication and the device must buffer any to-be-sent data until the host releases Clock. The Clock line must be continuously high for at least 50 microsecond

33、s before the device can begin to tra</p><p>　　As I mentioned in the previous section, the keyboard and mouse use a serial protocol with 11-bit frames. These bits are:</p><p>　　1 start bit. Thi

34、s is always 0.</p><p>　　8 data bits, least significant bit first.</p><p>　　1 parity bit (odd parity).</p><p>　　1 stop bit. This is always 1.</p><p>　　The keyboard/mous

35、e writes a bit on the Data line when Clock is high, and it is read by the host when Clock is low. Figures 2 and 3 illustrate this.</p><p>　　Figure 2: Device-to-host communication. The Data line changes st

36、ate when Clock is high and that data is valid when Clock is low. </p><p>　　Figure 3: Scan code for the "Q" key (15h) being sent from a keyboard to the computer. Channel A is the Clock signal; ch

37、annel B is the Data signal.</p><p><b>　　--- </b></p><p>　　The clock frequency is 10-16.7 kHz. The time from the rising edge of a clock pulse to a Data transition must be at least 5

38、 microseconds. The time from a data transition to the falling edge of a clock pulse must be at least 5 microseconds and no greater than 25 microseconds. </p><p>　　The host may inhibit communication at any

39、time by pulling the Clock line low for at least 100 microseconds. If a transmission is inhibited before the 11th clock pulse, the device must abort the current transmission and prepare to retransmit the current "ch

40、unk" of data when host releases Clock. A "chunk" of data could be a make code, break code, device ID, mouse movement packet, etc. For example, if a keyboard is interrupted while sending the second byte o

41、f a two-byte break code, it will need </p><p>　　Host-to-Device Communication: The packet is sent a little differently in host-to-device communication...</p><p>　　First of all, the PS/2 dev

42、ice always generates the clock signal. If the host wants to send data, it must first put the Clock and Data lines in a "Request-to-send" state as follows:</p><p>　　Inhibit communication by pulling

43、 Clock low for at least 100 microseconds.</p><p>　　Apply "Request-to-send" by pulling Data low, then release Clock.</p><p>　　The device should check for this state at intervals not to

44、exceed 10 milliseconds. When the device detects this state, it will begin generating Clock signals and clock in eight data bits and one stop bit. The host changes the Data line only when the Clock line is low, and data

45、 is read by the device when Clock is high. This is opposite of what occours in device-to-host communication.After the stop bit is received, the device will acknowledge the received byte by bringing the Data line low and

46、 </p><p>　　The host may abort transmission at time before the 11th clock pulse (acknowledge bit) by holding Clock low for at least 100 microseconds.</p><p>　　To make this process a little easier

47、 to understand, here's the steps the host must follow to send data to a PS/2 device:</p><p>　　Bring the Clock line low for at least 100 microseconds. 2) Bring the Data line low. 3) Release the Cloc

48、k line. 4) Wait for the device to bring the Clock line low. 5) Set/reset the Data line to send the first data bit 6) Wait for the device to bring Clock high. 7) Wait for the device to bring Clock low. 8) R

49、epeat steps 5-7 for the other seven data bits and the parity bit 9) Release the Data line. 10) Wait for the device to bring Data low. 11) Wait for the device to bring</p><p>　　Figure 3 shows this graphi

50、cally and Figure 4 separates the timing to show which signals are generated by the host, and which are generated by the PS/2 device. Notice the change in timing for the "ack" bit--the data transition occours w

51、hen the Clock line is high (rather than when it is low as is the case for the other 11 bits.)</p><p>　　Figure 3: Host-to-Device Communication. </p><p>　　Figure 4: Detailed host-to-device com

52、munication. </p><p>　　Referring to Figure 4, there's two time quantities the host looks for. (a) is the time it takes the device to begin generating clock pulses after the host initially takes the Clo

53、ck line low, which must be no greater than 15 ms. (b) is the time it takes for the packet to be sent, which must be no greater than 2ms. If either of these time limits is not met, the host should generate an error. Im

54、mediately after the "ack" is received, the host may bring the Clock line low to inhibit communication</p><p>　　REFERENCES</p><p>　　[1] Daemen J,Rijmen V.The Design of Rijndael:AES-The

55、 Advanced Encryption Standard. . 2002</p><p>　　[2] Prof Stephen A,Edwards.The PS/2 Keyboard and Mouse Interface［D］Columbia University,2009:65-67</p><p>　　[3] PS/2 Mouse/Keyboard Protocol, [OL]

56、.Adam Chapweske, Copyright 1999:112-120.</p><p>　　[4] Holtek Semiconductor Inc.PS/2 Mouse Controller Data Sheet. . 2003</p><p>　　[5] Adam Chapweske.PS/2 Mouse/Keyboard Protocol. http://www.din.d