單片機基礎畢業(yè)設計外文翻譯

1、<p>　　本科生畢業(yè)設計（論文）外文翻譯</p><p><b>　　畢業(yè)設計題目： </b></p><p>　　外文題目：Fundamentals of Single-chip Microcomputer</p><p>　　譯文題目：單片機基礎</p><p>　　學 院： 信息科學與工程學院

2、 </p><p>　　專業(yè)班級： 電子信息工程 0802班 </p><p>　　學生姓名： </p><p>　　指導教師： </p><p><b>　　外文原文</b></p>

3、<p>　　Fundamentals of Single-chip Microcomputer</p><p>　　Dr. Dobbs MacintoshJournal</p><p><b>　　Abstract</b></p><p>　　The single-chip microcomputer is the culminat

4、ion of both the development of the digital computer and the integrated circuit arguably the tow most significant inventions of the 20th century .</p><p>　　These tow types of architecture are found in single-

5、chip microcomputer. Some employ the split program/data memory of the Harvard architecture, shown in Fig.3-5A-1, others follow the philosophy, widely adapted for general-purpose computers and microprocessors, of making no

6、 logical distinction between program and data memory as in the Princeton architecture.</p><p>　　In general terms a single-chip microcomputer is characterized by the incorporation of all the units of a comput

7、er into a single device.</p><p>　　Keyword: Single-chip Microcomputer ROM RAM Programming Algorithm</p><p><b>　　Features</b></p><p>　　? Compatible with MCS-51? Produc

8、ts</p><p>　　? 4K Bytes of In-System Reprogrammable Flash Memory</p><p>　　– Endurance: 1,000 Write/Erase Cycles</p><p>　　? Fully Static Operation: 0 Hz to 24 MHz</p><p>

9、　　? Three-level Program Memory Lock</p><p>　　? 128 x 8-bit Internal RAM</p><p>　　? 32 Programmable I/O Lines</p><p>　　? Two 16-bit Timer/Counters</p><p>　　? Six Interru

10、pt Sources</p><p>　　? Programmable Serial Channel</p><p>　　? Low-power Idle and Power-down Modes</p><p>　　Description</p><p>　　The AT89C51 is a low-power, high-performa

11、nce CMOS 8-bit microcomputer with 4Kbytes of Flash programmable and erasable read only memory (PEROM). The deviceis manufactured using Atmel’s high-density nonvolatile memory technology and iscompatible with the industry

12、-standard MCS-51 instruction set and pinout. The on-chipFlash allows the program memory to be reprogrammed in-system or by a conventionalnonvolatile memory programmer. By combining a versatile 8-bit CPU with Flashon a mo

13、nolithic chip, the </p><p>　　Pin Configurations </p><p>　　Block Diagram</p><p>　　Pin Description</p><p><b>　　VCC</b></p><p>　　Supply voltage.&l

14、t;/p><p><b>　　GND</b></p><p><b>　　Ground.</b></p><p><b>　　Port 0</b></p><p>　　Port 0 is an 8-bit open-drain bi-directional I/O port. As

15、 anoutput port, each pin can sink eight TTL inputs. When 1sare written to port 0 pins, the pins can be used as highimpedanceinputs.</p><p>　　Port 0 may also be configured to be the multiplexed loworderaddres

16、s/data bus during accesses to external programand data memory. In this mode P0 has internalpullups.</p><p>　　Port 0 also receives the code bytes during Flash programming,and outputs the code bytes during pro

17、gramverification. External pullups are required during program verification.</p><p><b>　　Port 1</b></p><p>　　Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port

18、 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will

19、source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.</p><p><b>　　Port 2</b></p><p>　　Port

20、2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inp

21、uts. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during a

22、ccesses to external data memory that use 16-bit address</p><p><b>　　Port 3</b></p><p>　　Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can

23、 sink/source four TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL)

24、 because of the pullups.Port 3 also serves the functions of various special features of the AT89C51 as listed below:</p><p>　　Port 3 also receives some control signals for Flash programming</p><p&

25、gt;　　and verification.</p><p><b>　　ALE/PROG</b></p><p>　　Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is al

26、so the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, th

27、at one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With</p><p><b>　　PSEN</b></p><p&g

28、t;　　Program Store Enable is the read strobe to external program memory.When the AT89C51 is executing code from external programmemory, PSEN is activated twice each machine cycle, except that two PSEN activations are skip

29、ped during each access to external data memory.</p><p><b>　　EA/VPP</b></p><p>　　External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from ex

30、ternal program memory locations starting at 0000H up to FFFFH.Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This p

31、in also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.</p><p><b>　　XTAL1</b></p><p>　　Input to the inverting osci

32、llator amplifier and input to the internal clock operating circuit.</p><p><b>　　XTAL2</b></p><p>　　Output from the inverting oscillator amplifier.</p><p>　　Oscillator Ch

33、aracteristics</p><p>　　XTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal

34、 or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the extern

35、al clock signal, since the input to the internal clocking circuitry is through a divide-by-two f</p><p><b>　　Idle Mode</b></p><p>　　In idle mode, the CPU puts itself to sleep while a

36、ll the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any e

37、nabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution,from where it left off, up to two machine cycles before the int

38、ernal rese</p><p>　　Figure 1. Oscillator Connections</p><p>　　Figure 2. External Clock Drive Configuration</p><p>　　Power-down Mode</p><p>　　In the power-down mode, the

39、 oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only e

40、xit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long e

41、nough to allow the oscillator to </p><p>　　Program Memory Lock Bits</p><p>　　On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional

42、features listed in the table below.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, a

43、nd holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for th</p><p>　　Programming the Flash</p>&

44、lt;p>　　The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or

45、 a low-voltage (VCC) program enable signal. The low-voltage programming mode provides a convenient way to program the AT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventio

46、nal thirdparty Flash or EPROM programmers. The AT89C51 is shipped with</p><p>　　The AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip

47、 Flash Memory, the entire memory must be erased using the Chip Erase Mode.</p><p>　　Programming Algorithm: Before programming the AT89C51, the address, data and control signals should be set up according to

48、the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following steps.</p><p>　　1. Input the desired memory location on the address lines.</p><p>　　2. Inpu

49、t the appropriate data byte on the data lines.</p><p>　　3. Activate the correct combination of control signals.</p><p>　　4. Raise EA/VPP to 12V for the high-voltage programming mode.</p>

50、<p>　　5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms.Repeat steps 1 through 5, changing the address and data

51、for the entire array or until the end of the object file is reached.</p><p>　　Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of

52、the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time

53、 after a write cycle has been initiated.</p><p>　　Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to

54、 indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.</p><p>　　Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via

55、 the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.</p><p>　　Chip Erase: The entir

56、e Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the

57、 code memory can be re-programmed.</p><p>　　Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3

58、.7 must be pulled to a logic low. The values returned are as follows.</p><p>　　(030H) = 1EH indicates manufactured by Atmel</p><p>　　(031H) = 51H indicates 89C51</p><p>　　(032H) = F

59、FH indicates 12V programming</p><p>　　(032H) = 05H indicates 5V programming</p><p>　　Programming Interface</p><p>　　Every code byte in the Flash array can be written and the entire

60、array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion. All major programming vendors offer wo

61、rldwide support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision.</p><p><b>　　外文資料翻譯譯文</b></p><p><b>　　單

62、片機基礎</b></p><p>　　摘要：單片機是電腦和集成電路發(fā)展的巔峰，有據可查的是它們也是20世紀最</p><p><b>　　意義的兩大發(fā)明。</b></p><p>　　這兩種特性在單片機中得到了充分的體現。一些廠家用這兩種特性區(qū)分程序存儲器和數據存儲器在硬件中的特性，依據同樣的原理廣泛的適用于一般目的的電腦和微電腦，

63、一些廠家在程序內存和數據內存之間不區(qū)分，像普林斯頓特性。</p><p>　　關鍵字：單片機 只讀存貯器 隨機存取存儲器 編程方法</p><p><b>　　AT89C51</b></p><p><b>　　主要性能參數：</b></p><p>　　與MCS-51產品指令系統(tǒng)完全兼容<

64、;/p><p>　　4K字節(jié)可重檫寫Flash閃速存儲器</p><p><b>　　1000次檫寫周期</b></p><p>　　全靜態(tài)操作：0HZ-24MHZ</p><p><b>　　三級加密程序存儲器</b></p><p>　　128*8字節(jié)內部RAM</p&

65、gt;<p>　　32個可編程I/O口線</p><p>　　2個16位定時/記數器</p><p><b>　　6個中斷源</b></p><p>　　可編程串行UART通道</p><p>　　低功耗空閑和掉電模式</p><p><b>　　功能特性概述：</b

66、></p><p>　　AT89C51提供以下標準功能：4K字節(jié)Flash閃速存儲器，128字節(jié)內部RAM，32個I/O口線，兩個16位定時/記數器，一個5向量兩級中斷結構，一個全雙工串行通信口，片內振蕩器及時鐘電路。同時，AT89C51可降至0HZ的靜態(tài)邏輯操作，并支持兩種軟件可選的節(jié)電工作模式?？臻e方式停止CPU的工作，但允許RAM，定時/記數器，串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方式保存RAM中的內容

67、，但振蕩器停止工作直到下一個硬件復位。</p><p>　　AT89C51是美國ATMEL公司生產的低電壓，高性能CMOS8位單片機，片內含4k bytes的可反復擦寫的只讀程序存儲器（PEROM）和128 bytes的隨機存取數據存儲器（RAM），器件采用ATMEL公司的高密度、非易失性存儲技術生產，兼容標準MCS-51指令系統(tǒng)，片內置通用8位中央處理器（CPU）和Flash存儲單元，功能強大AT89C51單片

68、機可為您提供許多高性價比的應用場合，可靈活應用于各種控制領域。</p><p>　　AT89C51方框圖</p><p><b>　　引腳功能說明</b></p><p><b>　　·Vcc：電源電壓</b></p><p><b>　　·GND：地</b>

69、;</p><p>　　·P0 口：P0 口是一組8 位漏極開路型雙向I／O 口，也即地址／數據總線復用口。作為輸出口用時，每位能吸收電流的方式驅動8個TTL邏輯門電路，對端口寫“1”可作為高阻抗輸入端用。在訪問外部數據存儲器或程序存儲器時，這組口線分時轉換地址（低8位）和數據總線復用，在訪問期間激活內部上拉電阻。在FIash編程時，P0口接收指令字節(jié)，而在程序校驗時，輸出指令字節(jié)，校驗時，要求外接上拉

70、電阻。</p><p>　　·P1口：P1是一個帶內部上拉電阻的8位雙向I／O口，P1的輸出緩沖級可驅動（吸收或輸出電流）4個TTL邏輯門電路。對端口寫“1”，通過內部的上拉電阻把端口拉到高電平，此時可作輸入口。作輸入口使用時，因為內部存在上拉電阻，某個引腳被外部信號拉低時會輸出一個電流（IIL）。FIash編程和程序校驗期間，P1接收低8位地址。</p><p>　　·

71、;P2口：P2是一個帶有內部上拉電阻的8位雙向I／O口，P2的輸出緩沖級可驅動（吸收或輸出電流）4個TTL邏輯門電路。對端口寫“1”，通過內部的上拉電阻把端口拉到高電平，此時可作輸入口，作輸入口使用時，因為內部存在上拉電阻，某個引腳被外部信號拉低時會輸出一個電流（IIL）。在訪問外部程序存儲器或16位地址的外部數據存儲器（例如執(zhí)行MOVX@DPTR指令）時，P2口送出高8位地址數據。在訪問8 位地址的外部數據存儲器（如執(zhí)行MOVX@RI

72、 指令）時，P2 口線上的內容（也即特殊功能寄存器（SFR）區(qū)中R2寄存器的內容），在整個訪問期間不改變。Flash編程或校驗時，P2亦接收高位地址和其它控制信號</p><p>　　·P3口：P3口是一組帶有內部上拉電阻的8 位雙向I／O 口。P3 口輸出緩沖級可驅動（吸收或輸出電流）4 個TTL邏輯門電路。對P3 口寫入“1”時，它們被內部上拉電阻拉高并可作為輸入端口。作輸入端時，被外部拉低的P3

73、口將用上拉電阻輸出電流（IIL）。</p><p>　　P3口除了作為一般的I／O口線外，更重要的用途是它的第二功能，如下表所示：</p><p>　　P3口還接收一些用于Flash閃速存儲器編程和程序校驗的控制信號。</p><p>　　·RST：復位輸入。當振蕩器工作時，RST引腳出現兩個機器周期以上高電平將使單片機復位。</p><

74、;p>　　·ALE／PROG： 當訪問外部程序存儲器或數據存儲器時，ALE（地址鎖存允許）輸出脈沖用于鎖存地址的低8位字節(jié)。即使不訪問外部存儲器，ALE 仍以時鐘振蕩頻率的l／6 輸出固定的正脈沖信號，因此它可對外輸出時鐘或用于定時目的。要注意的是：每當訪問外部數據存儲器時將跳過一個ALE脈沖。對Flash存儲器編程期間，該引腳還用于輸入編程脈沖（PROG）。如有必要，可通過對特殊功能寄存器（SFR）區(qū)中的8EH單元的D

75、O 位置位，可禁止ALE 操作。該位置位后，只有一條MOVX和MOVC指令ALE才會被激活。此外，該引腳會被微弱拉高，單片機執(zhí)行外部程序時，應設置ALE無效。</p><p>　　·PSEN：程序儲存允許（PSEN）輸出是外部程序存儲器的讀選通信號，當AT89C51 由外部程序存儲器取指令（或數據）時，每個機器周期兩次PSEN有效，即輸出兩個脈沖。在此期間，當訪問外部數據存儲器，這兩次有效的PSEN信號

76、出現。</p><p>　　·EA／VPP：外部訪問允許。欲使CPU僅訪問外部程序存儲器（地址為0000H—FFFFH），EA端必須保持低電平（接地）。需注意的是：如果加密位LB1被編程，復位時內部會鎖存EA端狀態(tài)。如EA端為高電平（接VCC端），CPU則執(zhí)行內部程序存儲器中的指令。Flash存儲器編程時，該引腳加上+12V的編程允許電源Vpp，當然這必須是該器件是使用12V編程電壓Vpp。</p

77、><p>　　·XTAL1：振蕩器反相放大器的及內部時鐘發(fā)生器的輸入端。</p><p>　　·XTAL2：振蕩器反相放大器的輸出端。</p><p><b>　　·時鐘振蕩器：</b></p><p>　　AT89C5l 中有一個用于構成內部振蕩器的高增益反相放大器，引腳XTAL1 和XTAL

78、2 分別是該放大器的輸入端和輸出端。這個放大器與作為反饋元件的片外石英晶體或陶瓷諧振器一起構成自激振蕩器，振蕩電路參見圖5。外接石英晶體（或陶瓷諧振器）及電容C1、C2接在放大器的反饋回路中構成并聯振蕩電路。對外接電容C1、C2雖然沒有十分嚴格的要求，但電容容量的大小會輕微影響振蕩頻率的高低、振蕩器工作的穩(wěn)定性、起振的難易程序及溫度穩(wěn)定性，如果使用石英晶體，我們推薦電容使用30pF±10pF，而如使用陶瓷諧振器建議選擇40pF

79、±10F。用戶也可以采用外部時鐘。采用外部時鐘的電路如圖5右圖所示。這種情況下，外部時鐘脈沖接到XTAL1端，即內部時鐘發(fā)生器的輸入端，XTAL2則懸空。</p><p><b>　　圖1</b></p><p>　　石英晶體時：C1，C2＝30pF±10pF </p><p>　　陶瓷濾波器：C1，C2＝40pF±

80、;10pF</p><p><b>　　內部振蕩電路</b></p><p><b>　　圖2</b></p><p><b>　　外部時鐘驅動電路</b></p><p>　　由于外部時鐘信號是通過一個2分頻觸發(fā)器后作為內部時鐘信號的，所以對外部時鐘信號的占空比沒有特殊要求，

81、但最小高電平持續(xù)時間和最大的低電平持續(xù)時間應符合產品技術條件的要求。</p><p><b>　　·空閑節(jié)電模式：</b></p><p>　　AT89C51 有兩種可用軟件編程的省電模式，它們是空閑模式和掉電工作模式。這兩種方式是控制專用寄存器PCON（即電源控制寄存器）中的PD（PCON.1）和IDL（PCON.0）位來實現的。PD 是掉電模式，當PD=

82、1 時，激活掉電工作模式，單片機進入掉電工作狀態(tài)。IDL是空閑等待方式，當IDL=1，激活空閑工作模式，單片機進入睡眠狀態(tài)。如需同時進入兩種工作模式，即PD和IDL同時為1，則先激活掉電模式。在空閑工作模式狀態(tài)，CPU保持睡眠狀態(tài)而所有片內的外設仍保持激活狀態(tài)，這種方式由軟件產生。此時，片內RAM和所有特殊功能寄存器的內容保持不變?？臻e模式可由任何允許的中斷請求或硬件復位終止。終止空閑工作模式的方法有兩種，其一是任何一條被允許中斷的事件

83、被激活，IDL（PCON.0）被硬件清除，即刻終止空閑工作模式。程序會首先響應中斷，進入中斷服務程序，執(zhí)行完中斷服務程序并緊隨RETI（中斷返回）指令后，下一條要執(zhí)行的指令就是使單片機進入空閑模式那條指令后面的一條指令。其二是通過硬件復位也可將空閑工作模式終止。需要注意的是，當由硬件復位來終止空閑工作模式時，CPU 通常是從激活空閑模式那條指</p><p><b>　　·掉電模式：</

84、b></p><p>　　在掉電模式下，振蕩器停止工作，進入掉電模式的指令是最后一條被執(zhí)行的指令，片內RAM 和特殊功能寄存器的內容在終止掉電模式前被凍結。退出掉電模式的唯一方法是硬件復位，復位后將重新定義全部特殊功能寄存器但不改變RAM中的內容，在Vcc恢復到正常工作電平前，復位應無效，且必須保持一定時間以使振蕩器重啟動并穩(wěn)定工作。</p><p>　　·程序存儲器的加密

85、：</p><p>　　AT89C51 可使用對芯片上的3 個加密位LB1、LB2、LB3 進行編程（P）或不編程（U）來得到如下表所示的功能加密位保護功能表：</p><p>　　當加密位LB1 被編程時，在復位期間，EA端的邏輯電平被采樣并鎖存，如果單片機上電后一直沒有復位，則鎖存起的初始值是一個隨機數，且這個隨機數會一直保存到真正復位為止。為使單片機能正常工作，被鎖存的EA 電平值必

86、須與該引腳當前的邏輯電平一致。此外，加密位只能通過整片擦除的方法清除。</p><p>　　·Flash閃速存儲器的編程：</p><p>　　AT89C51 單片機內部有4k 字節(jié)的Flash PEROM，這個Flash 存儲陣列出廠時已處于擦除狀態(tài)（即所有存儲單元的內容均為FFH），用戶隨時可對其進行編程。編程接口可接收高電壓（+12V）或低電壓（Vcc）的允許編程信號。低電

87、壓編程模式適合于用戶在線編程系統(tǒng)，而高電壓編程模式可與通用EPROM編程器兼容。AT89C51單片機中，有些屬于低電壓編程方式，而有些則是高電壓編程方式，用戶可從芯片上的型號和讀取芯片內的名字節(jié)獲得該信息，見下表。</p><p>　　AT89C51的程序存儲器陣列是采用字節(jié)寫入方式編程的，每次寫入一個字節(jié)，要對整個芯片內的PEROM程序存儲器寫入一個非空字節(jié)，必須使用片擦除的方式將整個存儲器的內容清除。<

88、/p><p><b>　　·編程方法：</b></p><p>　　編程前，須按表6和圖6所示設置好地址、數據及控制信號。編程單元的地址加在P1口和P2口的P2.0－P2.3（11位地址范圍為0000H－0FFFH），數據從P0口輸入，引腳P2.6、P2.7和P3.6、P3.7的電平設置見表6，PSEN為低電平，RST保持高電平，EA／Vpp 引腳是編程電源的輸

89、入端，按要求加上編程電壓，ALE／PROG引腳輸入編程脈沖（負脈沖）。編程時，可采用4－20MHz的時鐘振蕩器，AT89C51編程方法如下：</p><p>　　1．在地址線上加上要編程單元的地址信號。</p><p>　　2．在數據線上加上要寫入的數據字節(jié)。</p><p>　　3．激活相應的控制信號。</p><p>　　4．在高電壓編程

90、方式時，將EA／Vpp端加上+12V編程電壓。</p><p>　　5．每對Flash存儲陣列寫入一個字節(jié)或每寫入一個程序加密位，加上一個ALE／PROG編程脈沖。改變編程單元的地址和寫入的數據，重復1—5步驟，直到全部文件編程結束。每個字節(jié)寫入周期是自身定時的，通常約為1.5ms。</p><p><b>　　·數據查詢：</b></p>&

91、lt;p>　　AT89C51單片機用數據查詢方式來檢測一個寫周期是否結束，在一個寫周期中，如需讀取最后寫入的那個字節(jié)，則讀出的數據的最高位（P0.7）是原來寫入字節(jié)最高位的反碼。寫周期完成后，有效的數據就會出現在所有輸出端上，此時，可進入下一個字節(jié)的寫周期，寫周期開始后，可在任意時刻進行數據查詢。</p><p>　　·Ready／Busy：字節(jié)編程的進度可通過RDY／BSY輸出信號監(jiān)測，編程期間

92、，ALE變?yōu)楦唠娖健癏”后P3.4（RDY／BSY）端電平被拉低，表示正在編程狀態(tài)（忙狀態(tài)）。編程完成后，P3.4變?yōu)楦唠娖奖硎緶蕚渚途w狀態(tài)。</p><p>　　·程序校驗：如果加密位LB1、LB2沒有進行編程，則代碼數據可通過地址和數據線讀回原編寫的數據，采用下圖的電路，程序存儲器的地址由P1 和P2 口的P2.0－P2.3輸入，數據由P0口讀出，P2.6、P2.7和P3.6、P3.7的控制信號見表

93、，PSEN保持低電平，ALE、EA和RST保持高電平。校驗時，P0口須接上10k左右的上拉電阻。</p><p>　　Flash 存儲器編程真值表</p><p>　　注：片擦除操作時要求PROG脈沖寬度為10ms</p><p><b>　　編程電路</b></p><p><b>　　校驗電路</b&