外文翻譯--系統(tǒng)芯片

1、<p><b>　　英文資料：</b></p><p>　　1 Introduction</p><p>　　The use of the system-on-chip ( SoC) technique allows for an unprecedented degree of miniaturization of rubidium atomic frequ

2、ency standards. A compact direct digital frequency synthesizer (DDFS) plays an important role in our miniaturized rubidium atomic frequency standards for modulated 5.3125MHz sine wave generation. DDFSs are able to genera

3、te single-phase or quadrature sinusoids with excellent frequency resolution, good spectral purity, very fast frequency switching[1 ], and phase continuity </p><p>　　where Δp is the phase increment word , j i

4、s the number of phase accumulator bits, fclk is the system clock frequency, and f out is t he output frequency. The previous constraint is required by the sampling theorem. The spectral purity of t he conventional DDFS i

5、s partly determined by the resolution of t he values stored in the ROM. It is desirable to increase the resolution of the ROM, but sometimes higher resolution means larger ROM size. However, the access speed and the maxi

6、mum output frequen</p><p>　　A 10bit on-chip current steering DAC is also implemented to convert the digital amplitude word to an equivalent analog amplitude.</p><p>　　2 Phase accumulator</p&g

7、t;<p>　　A 32bit phase accumulator is used in this DDFS. Figure 2 shows the block diagram of the phase accumulator. The phase accumulator is based on a 32bit ripple carry adder, with a string of full adders that op

8、erate on the same clock phase. The output s of the full adders have built-in registers, and the sum bits feed back internally to perform accumulation. A multiplexer(MUX) is used to select the phase increment word from th

9、e 32bit phase increment words stored in registers. In order to guarantee th</p><p>　　3 Phase to sine converter</p><p>　　3. 1 Sine function symmetry technique</p><p>　　The full-perio

10、d sine wave can be reconstructed with only π/2rad of the sine information by exploiting the quarter2wave symmetry of t he sine f unction. Figure 3 shows the details of this method. Since the most significant two bits of

11、the phase accumulator represent the quadrant of the sine function , the most significant bit (MSB) is used as the sign bit of the result, and the second most important bit (2nd MSB) is used to control whether the phase s

12、hould be increasing or decreasing[4 ]. The low</p><p>　　3. 2 Modified Sunderland technique</p><p>　　To reduce the ROM size, this DDFS uses the modified Sunderland technique based on simple trigo

13、nometric identities[ 5 ] . The phase address of a quarter</p><p>　　of a sine wave can be decomposed as φ= α+ β+ γ, where αis the MSBs ,βis the middle bits ,andγis the LSBs. The quarter-wave sine function is

14、given by where j is the number of the phase accumulator output bits. Equation (2) can be simplified further to</p><p>　　The information from the first term on the right of Eq. (3) is stored into a coarse

15、ROM. The second term on the right of Eq. (3) is stored into a fine ROM. This method works by introducing the 1/ 2L SBs offsets into the phase and amplitude of the sine ROM samples. However, significant savings in ROM siz

16、e can be realized due to the small magnitudes of β and γ relative to α. The 10bit phase data of accumulator outputs is divided into three parts in this design. Computer simulations determine the o</p><p>　　3

17、. 3 Sine2phase difference technique</p><p>　　The sine amplitude of the first term on the right of Eq. (3) is reduced using the sine phase difference technique, and two bits of the word length can be saved by

18、 only storing the difference of the sine amplitude and its phase.</p><p>　　3. 4 QLA technique</p><p>　　The QLA waveform is used to approximate the sine-phase difference , which is calculated usi

19、ng Eq.(4) . The QLA approximation can be expressed with following four expressions.</p><p>　　The data for 0 < (α+β) / 2j - 1 < 1/ 8 are generated through shifting down the phase (α+β) / 2j - 2 by 1bit.

20、 The data for 1/ 8 < (α+β) / 2j - 1 < 1/ 4 are generated through shifting down the phase (α+β) / 2j - 2 by 2bit and by changing the first and second MSBs of the phase to“10”. The data for 0 < (α+β) / 2j - 1 <

21、 1/ 4 and the data for 1/ 4 < (α+β) / 2j - 1 < 1/ 2 are symmetric .A complement is needed to reconstruct the symmetric waveform. Two bits of word length can be saved.cr (α+β) = y (α+β)</p><p>　　3. 5 QE

22、2ROM technique</p><p>　　Based on the continuity of the data that need compressing ,the ROM size of the DDFS can be further reduced using the QE-ROM technique. In this design, the second term on the right of

23、Eq. (3) and cr(α+β) are both compressed using the QE-ROM technique. The ROM size can be reduced to 2l ×m + 2a ×n bits using the QE-ROM technique, where l , m , a ,and n are, respectively, the length of the addr

24、ess of the quantization ROM, the length of the data in the quantization ROM ,the length of the address of t</p><p>　　(1) Find the maximum amplitude of the original data and figure out how many bits it takes

25、to represent this value. The maximum value of m can be represented by max m.</p><p>　　(2) Set m = max m.</p><p>　　(3) Set l = a , which is the address length of the original data.</p><

26、;p>　　(4) Calculate the quantized values.</p><p>　　(5) Calculate the errors between the original data and the quantization ROM data.</p><p>　　(6) Determine how many bits it takes to represent

27、these errors.</p><p>　　(7) Calculate t he total ROM size (2l ×m + 2a ×n) .</p><p>　　(8) Decrease l by 1. If l< 0 ,then go to (9) or else repeat the process from (4) to (7) .</p&g

28、t;<p>　　(9) Decrease m by 1. If m < 0 ,t hen go to (10) or else repeat the process from (4) to</p><p><b>　　(7).</b></p><p>　　(10) Determine the optimum values of the above

29、parameters that minimize the total ROM size.cr(α+β) is stored into a coarse ROM that is divided into a quantization ROM and an error ROM using the QE-ROM technique. The above calculations indicate that the minimum size o

30、f the coarse ROM for a 10bit output DDFS is 480bit (25 ×3 + 27 ×3 = 480) .The second term on the right of Eq. (3) is stored into a fine ROM, which is also divided into a quantization ROM and an error ROM using

31、the QE-ROM technique. T</p><p>　　3. 6 Architecture of the phase to sine converter</p><p>　　Figure 4 shows the block diagram of the phase to sine converter, which consists of complement, multiple

32、xers (MUXs ), ROMs, and adders. The complement are used to recover the full wave output from the quarter sine ROM by inverting the phase and amplitude appropriately. Four column MUXs and three adders are also required. F

33、igure 5 shows t he intermediate results during the approximation process. Figure 6 shows the sum of the data in the coarse ROM and the fine ROM and the final error . Figure 7 sh</p><p>　　The DDFS requires th

34、e smallest ROM compared with the DDFS using other compression methods in Table 1. Moreover, the ROM using this technique can produce a good spur level, as shown in Table 1.</p><p>　　4 Digital to analog conve

35、rter</p><p>　　In this design, an on-chip 10bit segmented current steering digital to analog converter (DAC) is implemented. This converter has 6bit thermometer-decoded most significant bits (MSBs) and 4bit t

36、hermometer-decoded least significant bits (LSBs). It is full thermometer-decoded to guarantee monotonicity and minimal glitches. The simplified DAC architecture is shown in Fig18. A clock buffer is included on the chip t

37、o obtain a good timing accuracy for the different clock signals used in the converter[8</p><p>　　5 Layout and experiment results</p><p>　　The compact DDFS has been fabricated using a 0.35μm CMOS

38、 process. The core area is 1.6mm ,which is almost 80 % smaller than the area of DDFSs with a complete 10bit sine ROM lookup table. A chip micrograph of the DDFS is shown in Fig110. As the figure shows , some other rubidi

39、um atomic frequency standard servo circuits are also implemented on the same chip besides the DDFS. Figure 11 (a) shows the output spectrum at f clk = 20MHz and f out = 625kHz. Figure 11 (a) shows t hat t he DDFS has an

40、exce</p><p>　　When the input system clock is operating at 20MHz, the DDFS only consumes 167mW at 3.3V. The measured results show that the most important specifications of this compact DDFS are better than sp

41、ecifications of previously used DDFS chips in our rubidium atomic frequency standard and the compact DDFS meets the requirements of rubidium atomic frequency standards completely. The size and power dissipation of the ru

42、bidium atomic frequency standard are significantly reduced and t he reliability of the </p><p>　　6 Conclusion</p><p>　　A compact DDFS used for SoC implementation of high resolution rubidium atom

43、ic frequency standards is implemented in this paper. The DDFS consists of two 32bit p hase registers, a 32bit phase accumulator , a phase to sine converter (768bit sine ROM),and a 10bit On-chip DAC. A DDFS chip with a co

44、re area of 1.6mm2 has been successfully fabricated using a standard 0.35μm CMOS process. The DDFS consumes 167mW at 3.3V and its SFDR is 61dB.</p><p><b>　　中文資料：</b></p><p><b>　

45、　1簡介</b></p><p>　　使用該系統(tǒng)芯片（ SoC ）技術(shù)可達(dá)到前所未有的程度即小型化銣原子頻率標(biāo)準(zhǔn)。小巧直接數(shù)字頻率合成器（直接數(shù)字頻率合成）在這中間起著重要的作用，我們的小型銣原子頻率標(biāo)準(zhǔn)正弦波調(diào)制5.3125MHz一代。 DDFSs能夠生成單相或正交的良好的頻率分辨率，優(yōu)異的頻譜純度，速度非?？旄哳l開關(guān)[ 1 ]和階段的連續(xù)性開關(guān)。一般而言，直接數(shù)字頻率合成器組成的一個(gè)階段累加器，一

46、個(gè)階段以正弦波轉(zhuǎn)換器（正弦波光盤和一個(gè)數(shù)模轉(zhuǎn)換器。在每一個(gè)時(shí)鐘脈沖，相位增量字頻率登記被添加到以前階段的價(jià)值，他在T階段累加器。該階段的價(jià)值產(chǎn)生使用模j滿溢從而使累加器到達(dá)階段。輸出頻率是T ，從而溢出，Δp是相增量字， J是數(shù)量相累加器位， fclk是系統(tǒng)時(shí)鐘頻率，和F是T了他的輸出頻率。以前的制約因素是所要求的采樣定理的頻譜純度的T的常規(guī)直接數(shù)字頻率合成器部分取決于該決議的T ，他的數(shù)值存儲(chǔ)在ROM中。這是可取的，增加的決議光盤，但

47、有時(shí)更高的分辨率是指規(guī)模較大的光盤。然而，存取速度和最大輸出頻率下降的光盤體積的增加。更大的光盤存儲(chǔ)也意味著更高的能耗，低可靠性，并大大增加成本。因此，重要的是減少的大小光盤的條件下，滿足高清晰</p><p>　　全期正弦波可重構(gòu)只有π/2rad的必要信息的利用quarter2wave對稱的T他正弦函數(shù)。因?yàn)樽钪匾膬蓚€(gè)比特的相位累加器代表象限的正弦函數(shù)，最重要的位（最高有效位）被用作符號(hào)位的結(jié)果，第二個(gè)最重要

48、的位（第2次最高有效位）是用來控制是否該階段應(yīng)增加或減少。低j - 2比特的相位累加器輸出被發(fā)送到一個(gè)補(bǔ)充所控制的第二最高有效位產(chǎn)生地址季度正弦光盤。斜坡的看到嘟H是倒第二象限所示，圖3 。波表的輸出季度正弦ROM是量化正弦波。全正弦波期間產(chǎn)生的輸出的第二次補(bǔ)充，其中包括異或門和一個(gè)逆變器。因此，光盤容量減少為代價(jià)的額外的邏輯。 3 .2桑德蘭改進(jìn)技術(shù)</p><p>　　為了減少光盤大小，這直接數(shù)字頻率合成器

49、使用修改桑德蘭技術(shù)的基礎(chǔ)上簡單的三角身份[ 5 ] 。逐步解決的四分之一個(gè)正弦波可以分解為φ = α + β + γ ，其中α是金錢服務(wù)行業(yè)， β是中東位，并且γ是的LSB s 。四分之一波正弦函數(shù)，給出了 在J的人數(shù)相累加器輸出位。方程（ 2 ）可進(jìn)一步簡化提供的資料，第一任期內(nèi)的權(quán)利的均衡器。 （ 3 ）儲(chǔ)存成粗光盤。在第二個(gè)任期的權(quán)利的均衡器。 （ 3 ）存儲(chǔ)到光盤罰款。這種方法的作品，介紹了1 / 2L辦學(xué)偏移到相位和振幅的正弦

50、光盤樣品。然而，大量的儲(chǔ)蓄在ROM規(guī)模，才能實(shí)現(xiàn)適當(dāng)?shù)男》鹊摩潞挺孟鄬τ讦?。 10位相位累加器輸出的數(shù)據(jù)分為三個(gè)部分在這一設(shè)計(jì)。計(jì)算機(jī)模擬確定最優(yōu)分割比α = 4 ， β = 3 ， γ = 3 [ 6 ] 。 3 .3 Sine2phase差異技術(shù)</p><p>　　正弦振幅的第一任期內(nèi)的權(quán)利的均衡器。 （ 3 ）減少使用正弦波相位差技術(shù)，和2位的字長可以保存的唯一的區(qū)別存儲(chǔ)的正弦振幅和相位。 3.

51、4 QLA技術(shù)</p><p>　　該QLA波形是用來近似正弦波相位差，這是計(jì)算的均衡器。 （ 4 ） 。該QLA近似可表示以下四種表現(xiàn)形式。 該數(shù)據(jù)為0 “ （ α + β ） / 2j - 1 ” 1月8日通過轉(zhuǎn)移產(chǎn)生了相（ α + β ） / 2j - 2 1bit 。據(jù)統(tǒng)計(jì)， 1月8日“ （ α + β ） / 2j - 1 ” 1月4日通過轉(zhuǎn)移產(chǎn)生了相（ α + β ） / 2j - 2的2位，并改變了

52、第一次和第二次服務(wù)行業(yè)的階段“ 10 ” 。該數(shù)據(jù)為0 “ （ α + β ） / 2j - 1 ” 1 / 4的數(shù)據(jù)和1 / 4 “ （ α + β ） / 2j - 1 ” 1 / 2是對稱的。 一種補(bǔ)充需要重建對稱波形。 2位字長可以保存。 鉻（ α + β ） =肽Y （ α + β ） - qla （ α + β ） （ 10 ） 馬克斯[鉻（ α + β ） ] ≈ 0126max [肽Y （ α + β ） ] （ 11

53、 ） 3 . 5 QE2ROM技術(shù)</p><p>　　基于連續(xù)性的數(shù)據(jù)，需要壓縮的光盤大小的直接數(shù)字頻率合成器可進(jìn)一步減少使用量子效率光盤技術(shù)。在此設(shè)計(jì)，第二個(gè)任期的權(quán)利的均衡器。 （ 3 ）和Cr （ α + β ）都是利用量子效率壓縮光盤技術(shù)。在ROM大小可降至2升×米+ 2A條× n的比特的量子效率利用光盤技術(shù)，其中L和N分別是長度的地址量化光盤，長度的數(shù)據(jù)在量化光盤，長度的解決原有

54、的數(shù)據(jù)，和長度中的數(shù)據(jù)錯(cuò)誤光盤?？赡苡袔捉M參數(shù)值，最大限度地減少了光盤的大小。找到這些，下面的算法是使用。 （1）尋找最大振幅的原始數(shù)據(jù)和數(shù)字，有多少位它代表這個(gè)值。最大值米可派最高米。 （2）設(shè)置m=最大值米。 （3）設(shè)置i= a ，這是地址長度的原始數(shù)據(jù)。 （4）計(jì)算量化值。 （5）計(jì)算錯(cuò)誤的原始數(shù)據(jù)和光盤的量化數(shù)據(jù)。 （6）確定有多少位代表這些錯(cuò)誤。 （7）計(jì)算他一共在光盤中所占的規(guī)模（ 2升×米+ 2A條

55、× n ）。 （8）減少了1升。如果升“ 0 ，然后轉(zhuǎn)到（9）或其他人重復(fù)上面的過程，從（4）至（7） 。 （9）減少了1米。如果米“ 0則轉(zhuǎn)到（10） ，否則重復(fù)上面的過程，從（4）至（7） 。 （10）確定最佳值的上述參數(shù)</p><p>　　3 . 6建筑階段正弦波轉(zhuǎn)換器</p><p>　　正弦波轉(zhuǎn)換器包括多路復(fù)用器（ MUXs ） ，只讀存儲(chǔ)器，和加法器。補(bǔ)體是用

56、來恢復(fù)全波輸出季度光盤的反相正弦波的相位和幅度適當(dāng)。四欄MUXs和三個(gè)附加器也需要。圖5結(jié)果顯示他在中間逼近的過程。圖6顯示的總和中的數(shù)據(jù)粗ROM和懲罰后ROM和最后的錯(cuò)誤。圖7顯示的相對位位置的數(shù)據(jù)用于重建正弦波。第一排的7位代表的階段，第二排的7位代表的四線逼近，第三排代表3bit量化光盤中的數(shù)據(jù)粗光盤，第四行代表3bit錯(cuò)誤- ROM的數(shù)據(jù)粗光盤，第五行代表1bit量化- ROM的數(shù)據(jù)光盤的罰款，第六行代表2位錯(cuò)誤- ROM的數(shù)據(jù)

57、光盤的罰款，并連續(xù)第七次代表9bit輸出加法。 </p><p><b>　　4數(shù)模轉(zhuǎn)換器</b></p><p>　　在這種設(shè)計(jì)，一個(gè)片上10位分割當(dāng)前指導(dǎo)數(shù)模轉(zhuǎn)換器（ DAC ）的執(zhí)行。這種轉(zhuǎn)換器有6位溫度計(jì)-解碼最重要的位（金錢服務(wù)行業(yè)）和4bit溫度計(jì)-解碼最重要的位（ LSBs ） 。這是充分溫度計(jì)-解碼保證單調(diào)性和最小的故障。簡化數(shù)模轉(zhuǎn)換器架構(gòu)中顯示Fig

58、18 。時(shí)鐘緩沖區(qū)包括在芯片上取得了良好的時(shí)間精度為不同的時(shí)鐘信號(hào)的轉(zhuǎn)換器中使用。降壓緩沖區(qū)中顯示Fig19還增加了在前面的每一個(gè)電流開關(guān)，以實(shí)現(xiàn)更好的動(dòng)態(tài)性能。不適當(dāng)?shù)拈_關(guān)電壓可能導(dǎo)致直接數(shù)字頻率合成器故障。通常情況下，開關(guān)電壓的CMOS電路是0.4V ，但我們選擇0.6V的，以確保開關(guān)可以有效履行。兩個(gè)重要參數(shù)的DACs'static性能的積分非線性（ INL ）和差動(dòng)非線性（ DNL ） ，其中涉及到的戰(zhàn)略布局的實(shí)施。發(fā)援