at89s51單片機(jī)外文翻譯

1、<p>　　The Description of AT89S51</p><p>　　1 General Description</p><p>　　The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K bytes of In-System Programmable Flas

2、h memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to

3、be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with In-System Programmable Flash on a monolithic c</p><p>　　The AT89S51 provides the followin

4、g standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five-vector two-level interrupt architecture, a full duplex serial port, on-chip osc

5、illator, and clock circuitry. In addition, the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. </p><p>　　The Idle Mode stop

6、s the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until

7、 the next external interrupt or hardware reset.</p><p><b>　　2 Ports</b></p><p>　　Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL

8、 inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memo

9、ry. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups </p><p>　　Port 1 is an 8-bit

10、 bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As

11、inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. </p><p>　　Port 1 also receives the low-order address bytes during Flash programming and ve

12、rification.</p><p>　　Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by

13、the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.Port 2 emits the high-order address byte during fetc

14、hes from external program memory and during accesses to external data memory that use 16-bit a</p><p>　　Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/s

15、ource four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) be

16、cause of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S51, </p><p>　　3 Special Function R

17、egisters</p><p>　　A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 3-1. </p><p>　　Table 3-1. AT89S51 SFR Map and Reset Values</p><p

18、>　　Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an ind

19、eterminate effect.</p><p>　　User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the

20、new bits will always be 0. </p><p>　　Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the five interrupt sources in the IP register.<

21、/p><p>　　Table 3-2. AUXR:Auxiliary Register</p><p>　　AUXR Address=8EH Reset Value=XXX00XX0b </p><p>　　Not Bit Addressable</p><

22、;p>　　– Reserved for future expansion</p><p>　　DISALE Disable/Enable ALE</p><p><b>　　DISALE</b></p><p>　　Operating Mode</p><p>　　0 ALE is e

23、mitted at a constant rate of 1/6 the oscillator frequency </p><p>　　1 ALE is active only during a MOVX or MOVC instruction </p><p>　　DISRTO Disable/Enable Reset-out</p><p&g

24、t;<b>　　DISRTO</b></p><p>　　0 Reset pin is driven High after WDT times out </p><p>　　1 Reset pin is input only </p><p>　　WDIDLE Disable/Enable WDT in I

25、DLE mode</p><p><b>　　WDIDLE</b></p><p>　　0 WDT continues to count in IDLE mode </p><p>　　1 WDT halts counting in IDLE mode</p><p>　　Dual

26、 Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SF

27、R AUXR1 selects DP0 and DPS = 1 selects DP1. The user should always initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register.</p><p>　　Power Off Flag: The Power O

28、ff Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to “1” during power up. It can be set and rest under software control and is not affected by reset.</p><p>　　Table 3-3. AUXR1:Auxiliary

29、 Register 1</p><p>　　4 Memory Organization</p><p>　　MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addr

30、essed.</p><p>　　4.1 Program Memory</p><p>　　If the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S51, if EA is connected to VCC, program fetches to

31、addresses 0000H through FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to external memory.</p><p>　　4.2 Data Memory</p><p>　　The AT89S51 implement

32、s 128 bytes of on-chip RAM. The 128 bytes are accessible via direct and indirect addressing modes. Stack operations are examples of indirect addressing, so the 128 bytes of data RAM are available as stack space.</p>

33、;<p>　　5 Watchdog Timer (One-time Enabled with Reset-out) </p><p>　　The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-b

34、it counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When th

35、e WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock f</p><p>　　5.1 Using the WDT</p><p>　　To enable

36、 the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14-b

37、it counter overflows when it reaches 16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT a

38、t least every 16383 machine cycles. To reset the WD</p><p>　　5.2 WDT DURING Power-down and Idle</p><p>　　In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-d

39、own mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt, which is enabled prior to entering Power-down mode.

40、When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S51 is reset. Exiting Power-down with an interrupt is significantly differen</p><p>　　With W

41、DIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.</p><p>　　6.Interrupts</p><p>　　The AT89S51 has a total of five interrupt vectors: two extern

42、al interrupts (INT0 and INT1), two timer interrupts (Timers 0 and 1), and the serial port interrupt. These interrupts are all shown in Figure 6-1. Each of these interrupt sources can be individually enabled or disabled b

43、y setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once.</p><p>　　Note that Table 6-1 shows that bit positions IE.6 and I

44、E.5 are unimplemented. User software should not write 1s to these bit positions, since they may be used in future AT89 products. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timer

45、s overflow. The values are then polled by the circuitry in the next cycle.</p><p>　　Table 6-1 Interrupt Enable(IE)Register</p><p>　　Figure 6-1 Interrupt Sources</p><p>　　7 Oscilla

46、tor Characteristics </p><p>　　XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 7-1. Either a quart

47、z crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 7-2. There are no requirements on the duty cycle o

48、f the external clock signal, since the input to the internal clocking circuitry is through a divide-by-</p><p>　　Figure 7-1 Oscillator Connections</p><p>　　Note: for Crystals</p><p&

49、gt;　　for Ceramic Resonators</p><p>　　Figure 7-2 External Clock Drive Configuration</p><p>　　8 Idle Mode </p><p>　　In idle mode, the CPU puts itself to sleep while all the on-chip p

50、eripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special function registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt

51、 or by a hardware reset. </p><p>　　Note that when idle mode is terminated by a hardware reset, the device normally resumes pro-gram execution from where it left off, up to two machine cycles before the inter

52、nal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle

53、 mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to</p><p>　　9 Power-down Mode</p><p>　　In the Power-down mode, the oscillator is stopped

54、, and the instruction that invokes Power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power-down mode is terminated. Exit from Power-down mode can be

55、 initiated either by a hardware reset or by activation of an enabled external interrupt (INT0 or INT1). Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restor

56、ed to its n</p><p>　　Table 9-1 Status of External Pins During Idle and Power-down Modes</p><p><b>　　AT89S51概述</b></p><p><b>　　1 一般概述 </b></p><p&g

57、t;　　該AT89S51是一個(gè)低功耗，高性能CMOS 8位微控制器,可在4K字節(jié)的系統(tǒng)內(nèi)編程的閃存存儲(chǔ)器。該設(shè)備是采用Atmel的高密度、非易失性存儲(chǔ)器技術(shù)和符合工業(yè)標(biāo)準(zhǔn)的80C51指令集和引腳。芯片上的Flash程序存儲(chǔ)器在系統(tǒng)中可重新編程或常規(guī)非易失性內(nèi)存編程 。通過(guò)結(jié)合通用8位中央處理器的系統(tǒng)內(nèi)可編程閃存的單芯片， AT89S51是一個(gè)功能強(qiáng)大的微控制器提供了高度靈活的和具有成本效益的解決辦法，可在許多嵌入式控制中應(yīng)用。 <

58、/p><p>　　在AT89S51提供以下標(biāo)準(zhǔn)功能： 4K字節(jié)的Flash閃存 ， 128字節(jié)的RAM ， 32個(gè) I / O線，看門(mén)狗定時(shí)器，兩個(gè)數(shù)據(jù)指針，兩個(gè)16位定時(shí)器/計(jì)數(shù)器， 5向量?jī)杉?jí)中斷結(jié)構(gòu)，全雙工串行端口，片上振蕩器和時(shí)鐘電路。此外， AT89S51設(shè)計(jì)了可降至零頻率的靜態(tài)邏輯操作和支持兩種軟件可選的節(jié)電工作模式。</p><p>　　在空閑模式下停止CPU的工作，但允許RAM

59、 、定時(shí)器/計(jì)數(shù)器、串行接口和中斷系統(tǒng)繼續(xù)運(yùn)行。掉電模式保存RAM中的內(nèi)容，停止振蕩器工作并禁止其它所有部件工作，直到下一個(gè)外部中斷或硬件復(fù)位。 </p><p><b>　　2 端口</b></p><p>　　P0端口是一個(gè)8位漏極開(kāi)路雙向I / O端口。作為一個(gè)輸出端口，每個(gè)引腳可驅(qū)動(dòng)8個(gè)TTL輸入。對(duì)端口寫(xiě)“1”可作為高阻抗輸入端用。在訪問(wèn)外部程序和數(shù)據(jù)存儲(chǔ)器

60、時(shí)，P0端口也可以配置為復(fù)低階地址/數(shù)據(jù)總線。在訪問(wèn)期間激活內(nèi)部上拉電阻。在Flash編程時(shí)，PO端口接收指令字節(jié)，而在程序校驗(yàn)時(shí)，輸出指令字節(jié)，同時(shí)要求外接上拉電阻。 </p><p>　　P1端口是一個(gè)帶內(nèi)部上拉電阻的8位雙向I /O端口。P1端口的輸出緩沖級(jí)可以驅(qū)動(dòng)四個(gè)TTL輸入。對(duì)端口寫(xiě)“1”，通過(guò)內(nèi)部的上拉電阻把端口拉到高電平，此時(shí)可作為輸入口。作為輸入口時(shí)，因?yàn)閮?nèi)部存在上拉電阻，某個(gè)引腳被外部信號(hào)拉低

61、時(shí)會(huì)輸出一個(gè)電流（IIL），F(xiàn)lash編程和程序校驗(yàn)期間，P1接收低8位地址。</p><p>　　P2端口是一個(gè)帶有內(nèi)部上拉電阻的8位雙向I/O端口。P2端口的輸出緩沖級(jí)可驅(qū)動(dòng)（吸收或輸出電流）4個(gè)TTL輸入。對(duì)端口寫(xiě)“1”，通過(guò)內(nèi)部的上拉電阻把端口拉到高電平，此時(shí)可作輸入口。當(dāng)作輸入口使用時(shí)，因?yàn)閮?nèi)部存在上拉電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流（IIL）。在訪問(wèn)外部程序存儲(chǔ)器或16位地址的外部數(shù)據(jù)存儲(chǔ)

62、器（例如執(zhí)行 MOVX @ DPTR指令 ）時(shí)，P2端口送出高8位地址數(shù)據(jù)。 在訪問(wèn)8位地址的外部數(shù)據(jù)存儲(chǔ)器（例如執(zhí)行MOVX@Ri指令）時(shí)，P2端口上的內(nèi)容（即特殊功能寄存器（SFR)區(qū)中P2寄存器的內(nèi)容），在整個(gè)訪問(wèn)期間不變。Flash編程或校驗(yàn)時(shí)，P2也可接收高位地址和其它控制信號(hào)。</p><p>　　P3端口是一組帶有內(nèi)部上拉電阻的8位雙向I/O端口。P3端口輸出緩沖級(jí)可驅(qū)動(dòng)（吸收或輸出電流）4個(gè)TTL

63、邏輯門(mén)電路。對(duì)P3端口寫(xiě)入“1”時(shí)，他們被內(nèi)部上拉電阻拉高并作為輸入端口。當(dāng)作輸入端時(shí)，被外部拉低的P2端口將用上拉電阻輸出電流（IIL）．Ｐ３端口還接收一些用于Flash閃存編程和程序校驗(yàn)的控制信號(hào)。P3端口可以采用AT89S51的</p><p>　　各種特殊功能，如下表所示。</p><p>　　3 特殊功能寄存器 </p><p>　　特殊功能寄存器（SFR

64、）的片內(nèi)空間分布如表3-1所示。</p><p>　　表3-1 AT89S51特殊功能寄存器分布圖及復(fù)位值</p><p>　　值得注意的是，這些地址并沒(méi)有全部占用，沒(méi)有占用的地址也不可使用，讀這些地址將得到一個(gè)隨意的數(shù)值。而寫(xiě)這些地址單元不能得到預(yù)期的結(jié)果。</p><p>　　不要用軟件訪問(wèn)這些未定義的單元，這些單元是留作以后產(chǎn)品擴(kuò)展用途的，復(fù)位后這些新的位將

65、為0。</p><p>　　中斷寄存器：各個(gè)中斷控制位于IE寄存器，5個(gè)中斷源的中斷優(yōu)先級(jí)控制位于IP寄存器。</p><p>　　表3-2 AUXR輔助寄存器</p><p>　　雙數(shù)據(jù)指針寄存器：為了便于訪問(wèn)內(nèi)部和外部數(shù)據(jù)存儲(chǔ)器，提供兩個(gè)16位數(shù)據(jù)指針寄存器： DP0位于SFR（特殊功能寄存器）區(qū)塊中的地址82H - 83H和DP1位于84H - 85H 。

66、當(dāng)SFR中的位DPS = 0選擇DP0，而DPS=1則選擇DP1 。用戶應(yīng)在訪問(wèn)相應(yīng)的數(shù)據(jù)指針寄存器前初始化DPS位。</p><p>　　電源空閑標(biāo)志：電源空閑標(biāo)志（POF）在特殊功能寄存器SFR中PCON的第四位（PCON.4）,電源打開(kāi)時(shí)POF置“1”，它可由軟件設(shè)置睡眠轉(zhuǎn)臺(tái)并不為復(fù)位所影響。</p><p>　　表3-3 AUXR輔助寄存器1</p><p&g

67、t;<b>　　4 存儲(chǔ)器結(jié)構(gòu)</b></p><p>　　MCS-51單片機(jī)內(nèi)核采用程序存儲(chǔ)器和數(shù)據(jù)存儲(chǔ)器空間分開(kāi)的結(jié)構(gòu)，均具有64KB外部程序和數(shù)據(jù)的尋址空間。</p><p>　　4.1 程序存儲(chǔ)器 </p><p>　　如果的EA引腳接地（GND），全部程序都可以執(zhí)行外部存儲(chǔ)器。在AT89S51 ，如果EA連接到電源+（VCC） ，程序

68、首先執(zhí)行地址從0000H到FFFH內(nèi)部存儲(chǔ)器，在執(zhí)行地址從1000H到FFFFH的外部程序存儲(chǔ)器。</p><p>　　4.2 數(shù)據(jù)存儲(chǔ)器 </p><p>　　AT89S51具有128字節(jié)的內(nèi)部RAM 。 這128字節(jié)都可以通過(guò)直接和間接尋址方式訪問(wèn)，堆棧操作可利用間接尋址方式進(jìn)行，因此， 128字節(jié)都可以可作為堆?？臻g。</p><p>　　5 看門(mén)狗定時(shí)器 （

69、WDT）</p><p>　　看門(mén)狗定時(shí)器（WDT）是為了解決CPU程序運(yùn)行時(shí)可能進(jìn)入混亂或死循環(huán)而設(shè)置，它由一個(gè)14bit計(jì)數(shù)器和看門(mén)狗定時(shí)器復(fù)位SFR（WDTRST）構(gòu)成。外部復(fù)位時(shí)，看門(mén)狗定時(shí)器（WDT）默認(rèn)為關(guān)閉狀態(tài)，要打開(kāi)WDT，用戶必須按順序?qū)?1EH和0E1H寫(xiě)到WDTRST寄存器（SFR地址為0A6H），當(dāng)啟動(dòng)了WDT，它會(huì)隨警惕振蕩器在每個(gè)機(jī)器周期計(jì)數(shù)，除了硬件復(fù)位或WDT溢出復(fù)位外沒(méi)有其它方法

70、關(guān)閉WDT，當(dāng)WDT溢出，將使RST引腳輸出高電平的復(fù)位脈沖。</p><p>　　5.1使用看門(mén)狗定時(shí)器（WDT）</p><p>　　用戶在打開(kāi)WDT時(shí)，需要按次序?qū)?1EH和0E1H寫(xiě)到WDTRST寄存器(SFR的地址為0A6H)，當(dāng)WDT打開(kāi)后，需要在一定的時(shí)候?qū)?1EH和0E1H寫(xiě)道WDTRST寄存器以避免WDT計(jì)數(shù)溢出。14位WDT計(jì)數(shù)器達(dá)到16383（3FFFH），WDT將溢

71、出并使用器件復(fù)位。WDT打開(kāi)時(shí)，它會(huì)隨著晶體振蕩器在每個(gè)機(jī)器周期計(jì)數(shù)，這意味著用戶必須在小于每個(gè)16383機(jī)器周期內(nèi)復(fù)位WDT，也即寫(xiě)01EH和0E1H到WDTRST寄存器，WDTRST為只寫(xiě)寄存器。WDT計(jì)數(shù)器既不可讀也不可寫(xiě)，當(dāng)WDT溢出時(shí)，通常將使RST引腳輸出高電平的復(fù)位脈沖。復(fù)位脈沖持續(xù)時(shí)間為98xTosc，而Tosc=1/Fosc(晶體振蕩頻率)。為使WDT工作最優(yōu)化，必須在合適的程序代碼時(shí)間段周期地復(fù)位WDT防止WDT溢出

72、。</p><p>　　5.2掉電和空閑模式下的WDT</p><p>　　掉電時(shí)期，晶體振蕩停止，看門(mén)狗定時(shí)器也停止。掉電模式下，用戶不嗯那個(gè)在復(fù)位看門(mén)狗定時(shí)器。有兩種方法可以推出掉電模式：硬件復(fù)位或通過(guò)激活外部中斷，當(dāng)硬件復(fù)位退出掉電模式時(shí)，處理看門(mén)狗定時(shí)器可像通常的上電復(fù)位一樣。當(dāng)由中斷退出掉電模式時(shí)則有所不同，中斷低電平狀態(tài)持續(xù)到晶體振蕩穩(wěn)定，當(dāng)中斷電平變?yōu)楦唠娖绞录纯上鄳?yīng)中斷服務(wù)

73、。以防止中斷誤復(fù)位，當(dāng)器件復(fù)位，中斷引腳持續(xù)為低時(shí)，看門(mén)狗定時(shí)器并未開(kāi)始計(jì)數(shù)，知道中斷引腳被拉高時(shí)為止。這為在掉電模式下的中斷執(zhí)行中斷服務(wù)程序而設(shè)置。為保證看門(mén)狗定時(shí)器在退出掉電模式時(shí)極端情況下不溢出，最好在進(jìn)入掉電模式前復(fù)位看門(mén)狗定時(shí)器。在進(jìn)入空閑模式前，看門(mén)狗定時(shí)器打開(kāi)時(shí)，WDT是否繼續(xù)計(jì)數(shù)由SFR中的AUXR的WDIDLE位決定，在IDLE期間（位WDIDLE=0）默認(rèn)狀態(tài)是繼續(xù)計(jì)數(shù)。為防止AT89S51從空閑模式中復(fù)位，用戶應(yīng)該

74、周期性地設(shè)置定時(shí)器，重新進(jìn)入空閑模式。</p><p>　　當(dāng)WDIDLE位被置位，在空閑模式中看門(mén)狗定時(shí)器將停止計(jì)數(shù)，直到從空閑(IDLE)模式中退出重新開(kāi)始計(jì)數(shù)。</p><p><b>　　6 中斷</b></p><p>　　AT89S51共有五個(gè)中斷向量：兩個(gè)外部中斷（ INT0和INT1 ） ，兩個(gè)定時(shí)器中斷（Timer0和Tim

75、er1)和一個(gè)串行中斷。這些中斷都如圖6-1 。這些中斷源各自的禁止和使能位參見(jiàn)特殊功能寄存器的IE。IE也包含總中斷控制位EA，EA清0，將關(guān)閉所有中斷。</p><p>　　值得注意的是表6-1中的IE.6和IE.5沒(méi)有定義，用戶不要訪問(wèn)這些位，它是保留為以后的AT89產(chǎn)品擴(kuò)展用途。定時(shí)器0和定時(shí)器1的中斷標(biāo)志TF0和TF1，它是定時(shí)器溢出時(shí)的S5P2時(shí)序周期被置位，該標(biāo)志保留至下個(gè)時(shí)序周期。</p&g

76、t;<p>　　表6-1 中斷控制寄存器（IE）</p><p>　　圖6-1 中斷源方框圖</p><p><b>　　7 振蕩器特性 </b></p><p>　　AT89S51中有一個(gè)用于構(gòu)成內(nèi)部振蕩器的高增益反相放大器，引腳XTAL1和XTAL2分別是該放大器的輸入端和輸出端。如圖7-1所示。外接石英晶體或陶瓷諧振器

77、都可以使用于反饋元件。用戶也可以采用外部時(shí)鐘，在這種情況下，外部時(shí)鐘接到XTAL1端，即內(nèi)部時(shí)鐘發(fā)生器的輸入端，XTAL2則懸空，如圖7-2所示。由于外部時(shí)鐘信號(hào)是通過(guò)一個(gè)2分頻觸發(fā)器后作為內(nèi)部時(shí)鐘信號(hào)的，所以對(duì)外部時(shí)鐘信號(hào)的占空比沒(méi)有特殊要求，但是最小高電平持續(xù)時(shí)間和最大的低電平時(shí)序時(shí)間應(yīng)符合產(chǎn)品技術(shù)條件的要求。</p><p>　　圖7-1 內(nèi)部振蕩電路</p><p>　　注意：石

78、英晶體時(shí)， </p><p><b>　　陶瓷濾波器，</b></p><p>　　圖7-2 外部時(shí)鐘驅(qū)動(dòng)電路</p><p><b>　　8 空閑模式 </b></p><p>　　在空閑工作模式狀態(tài)， CPU保持睡眠狀態(tài)而所有片內(nèi)的外設(shè)仍然保持激活狀態(tài)，這種方式由軟件產(chǎn)生。此時(shí)，片

79、內(nèi)RAM和所有特殊功能寄存器的內(nèi)特那個(gè)保持不變，空閑模式可由任何語(yǔ)序中斷的請(qǐng)求或硬件復(fù)位終止。</p><p>　　需要注意的是，當(dāng)由硬件復(fù)位來(lái)終止空閑工作模式時(shí)，CPU通常是從激活空閑模式那條指令的下一條指令開(kāi)始繼續(xù)執(zhí)行程序的，要完成內(nèi)部復(fù)位操作，硬件復(fù)位脈沖要保持兩個(gè)機(jī)器周期有效，在這種情況下，內(nèi)部禁止CPU訪問(wèn)片內(nèi)RAM,而允許訪問(wèn)其他端口。為了避免在復(fù)位結(jié)束時(shí)可能對(duì)端口產(chǎn)生意外寫(xiě)入，激活空閑模式的那條指令

80、的后一條指令不應(yīng)該是一條對(duì)端口或外部存儲(chǔ)器的寫(xiě)入指令。</p><p><b>　　9 掉電模式</b></p><p>　　在掉線模式下，振蕩器停止工作，進(jìn)入掉電模式的指令是最后一條被執(zhí)行的指令，片內(nèi)RAM和特殊功能寄存器的內(nèi)容在終止掉電模式前被凍結(jié)。退出掉電模式的方法是硬件復(fù)位或由處于使能狀態(tài)的外中斷INT0和INT1激活。復(fù)位后將重新定義全部特殊功能寄存器，但不