單片機外文文獻和中文翻譯

1、<p>　　Validation and Testing of Design Hardening for Single Event Effects Using the 8051 Microcontroller</p><p><b>　　Abstract </b></p><p>　　With the dearth of dedicated radiatio

2、n hardened foundries, new and novel techniques are being developed for hardening designs using non-dedicated foundry services. In this paper, we will discuss the implications of validating these methods for the single ev

3、ent effects (SEE) in the space environment. Topics include the types of tests that are required and the design coverage (i.e., design libraries: do they need validating for each application?). Finally, an 8051 microcontr

4、oller core from NASA In</p><p>　　Index Terms </p><p>　　Single Event Effects, Hardened-By-Design, microcontroller, radiation effects.</p><p>　　I. INTRODUCTION</p><p>　　N

5、ASA constantly strives to provide the best capture of science while operating in a space radiation environment using a minimum of resources [1,2]. With a relatively limited selection of radiation-hardened microelectronic

6、 devices that are often two or more generations of performance behind commercial state-ofthe-art technologies, NASA’s performance of this task is quite challenging. One method of alleviating this is by the use of commerc

7、ial foundry alternatives with no or minimally invasive desi</p><p>　　However, one question still exists: traditional radiation-hardened devices have lot and/or wafer radiation qualification tests performed;

8、what types of tests are required for HBD validation?</p><p>　　II. TESTING HBD DEVICES CONSIDERATIONS</p><p>　　Test methodologies in the United States exist to qualify individual devices through

9、standards and organizations such as ASTM, JEDEC, and MIL-STD- 883. Typically, TID (Co-60) and SEE (heavy ion and/or proton) are required for device validation. So what is unique to HBD devices?</p><p>　　As o

10、pposed to a “regular” commercial-off-the-shelf (COTS) device or application specific integrated circuit (ASIC) where no hardening has been performed, one needs to determine how validated is the design library as opposed

11、to determining the device hardness. That is, by using test chips, can we “qualify” a future device using the same library?</p><p>　　Consider if Vendor A has designed a new HBD library portable to foundries B

12、 and C. A test chip is designed, tested, and deemed acceptable. Nine months later a NASA flight project enters the mix by designing a new device using Vendor A’s library. Does this device require complete radiation quali

13、fication testing? To answer this, other questions must be asked.</p><p>　　How complete was the test chip? Was there sufficient statistical coverage of all library elements to validate each cell? If the new N

14、ASA design uses a partially or insufficiently characterized portion of the design library, full testing might be required. Of course, if part of the HBD was relying on inherent radiation hardness of a process, some of th

15、e tests (like SEL in the earlier example) may be waived. </p><p>　　Other considerations include speed of operation and operating voltage. For example, if the test chip was tested statically for SEE at a powe

16、r supply voltage of 3.3V, is the data applicable to a 100 MHz operating frequency at 2.5V? Dynamic considerations (i.e., nonstatic operation) include the propagated effects of Single Event Transients (SETs). These can be

17、 a greater concern at higher frequencies.</p><p>　　The point of the considerations is that the design library must be known, the coverage used during testing is known, the test application must be thoroughly

18、 understood and the characteristics of the foundry must be known. If all these are applicable or have been validated by the test chip, then no testing may be necessary. A task within NASA’s Electronic Parts and Packaging

19、 (NEPP) Program was performed to explore these types of considerations.</p><p>　　III. HBD TECHNOLOGY EVALUATION USING THE 8051 MICROCONTROLLER</p><p>　　With their increasing capabilities and low

20、er power consumption, microcontrollers are increasingly being used in NASA and DOD system designs. There are existing NASA and DoD programs that are doing technology development to provide HBD. Microcontrollers are one s

21、uch vehicle that is being investigated to quantify the radiation hardness improvement. Examples of these programs are the 8051 microcontroller being developed by Mission Research Corporation (MRC) and the IAμE (the focus

22、 of this study). A</p><p>　　The 8051 microcontroller is an industry standard architecture that has broad acceptance, wide-ranging applications and development tools available. There are numerous commercial v

23、endors that supply this controller or have it integrated into some type of system-on-a-chip structure. Both MRC and IAμE chose this device to demonstrate two distinctly different technologies for hardening. The MRC examp

24、le of this is to use temporal latches that require specific timing to ensure that single event effect</p><p>　　The objective of this work is the technology evaluation of the CULPRiT process [3] from IAμE. Th

25、e process has been baselined against two other processes, the standard 8051 commercial device from Intel and a version using state-of-the-art processing from Dallas Semiconductor. By performing this side-by-side comparis

26、on, the cost benefit, performance, and reliability trade study can be done.</p><p>　　In the performance of the technology evaluation, this task developed hardware and software for testing microcontrollers. A

27、 thorough process was done to optimize the test process to obtain as complete an evaluation as possible. This included taking advantage of the available hardware and writing software that exercised the microcontroller su

28、ch that all substructures of the processor were evaluated. This process is also leading to a more complete understanding of how to test complex structures, su</p><p>　　IV. TEST DEVICES</p><p>　　

29、Three devices were used in this test evaluation. The first is the NASA CULPRiT device, which is the primary device to be evaluated. The other two devices are two versions of a commercial 8051, manufactured by Intel and D

30、allas Semiconductor, respectively.</p><p>　　The Intel devices are the ROMless, CMOS version of the classic 8052 MCS-51 microcontroller. They are rated for operation at +5V, over a temperature range of 0 to 7

31、0 °C and at a clock speeds of 3.5 MHz to 24 MHz. They are manufactured in Intel’s P629.0 CHMOS III-E process.</p><p>　　The Dallas Semiconductor devices are similar in that they are ROMless 8052 microcon

32、trollers, but they are enhanced in various ways. They are rated for operation from 4.25 to 5.5 Volts over 0 to 70 °C at clock speeds up to 25 MHz. They have a second full serial port built in, seven additional inter

33、rupts, a watchdog timer, a power fail reset, dual data pointers and variable speed peripheral access. In addition, the core is redesigned so that the machine cycle is shortened for most instructions, re</p><p&

34、gt;　　The CULPRiT technology device is a version of the MSC-51 family compatible C8051 HDL core licensed from the Ultra Low Power (ULP) process foundry. The CULPRiT technology C8051 device is designed to operate at a su

35、pply voltage of 500 mV and includes an on-chip input/output signal level-shifting interface with conventional higher voltage parts. The CULPRiT C8051 device requires two separate supply voltages; the 500 mV and the desir

36、ed interface voltage. The CULPRiT C8051 is ROMless and is intende</p><p>　　V. TEST HARDWARE</p><p>　　The 8051 Device Under Test (DUT) was tested as a component of a functional computer. Aside fr

37、om DUT itself, the other components</p><p>　　of the DUT computer were removed from the immediate area of the irradiation beam. A small card (one per DUT package type) with a unique hard-wired identifier byte

38、 contained the DUT, its crystal, and bypass capacitors (and voltage level shifters for the CULPRiT DUTs). This "DUT Board" was connected to the "Main Board" by a short 60-conductor ribbon cable. The M

39、ain Board had all other components required to complete the DUT Computer, including some which nominally are not necessary in some designs</p><p>　　The DUT Computer and the Test Control Computer were connect

40、ed via a serial cable and communications were established between the two by the Controller (that runs custom designed serial interface software). This Controller software allowed for commanding of the DUT, downloading D

41、UT Code to the DUT, and real-time error collection from the DUT during and post irradiation. A 1 Hz signal source provided an external watchdog timing signal to the DUT, whose watchdog output was monitored via an oscill

42、o</p><p>　　VI. TEST SOFTWARE </p><p>　　The 8051 test software concept is straightforward. It was designed to be a modular series of small test programs each exercising a specific part of the DUT

43、. Since each test was stand alone, they were loaded independently of each other for execution on the DUT. This ensured that only the desired portion of the 8051 DUT was exercised during the test and helped pinpoint locat

44、ion of errors that occur during testing. All test programs resided on the controller PC until loaded via the serial interface</p><p>　　All test programs implemented:</p><p>　　? An external Unive

45、rsal Asynchronous Receive and Transmit device (UART) for transmission of error information and communication to controller computer.</p><p>　　? An external real-time clock for data error tag.</p><

46、p>　　? A watchdog routine designed to provide visual verification of 8051 health and restart test code if necessary.</p><p>　　? A "foul-up" routine to reset program counter if it wanders out of c

47、ode space.</p><p>　　? An external telemetry data storage memory to provide backup of data in the event of an interruption in data transmission.</p><p>　　The brief description of each of the soft

48、ware tests used is given below. It should be noted that for each test, the returned telemetry (including time tag) was sent to both the test controller and the telemetry memory, giving the highest reliability that all da

49、ta is captured.</p><p>　　Interrupt – This test used 4 of 6 available interrupt vectors (Serial, External, Timer0 Overflow, and Timer1 Overflow) to trigger routines that sequentially modified a value in the a

50、ccumulator which was periodically compared to a known value. Unexpected values were transmitted with register information. </p><p>　　Logic – This test performed a series of logic and math computations and pr

51、ovided three types of error identifications: 1) addition/subtraction, 2) logic and 3) multiplication/division. All miscompares of computations and expected results were transmitted with other relevant register informatio

52、n. </p><p>　　Memory – This test loaded internal data memory at locations D:0x20 through D:0xff (or D:0x20 through D:0x080 for the CULPRiT DUT), indirectly, with an 0x55 pattern. Compares were performed conti

53、nuously and miscompares were corrected while error information and register values were transmitted. </p><p>　　Program Counter -The program counter was used to continuously fetch constants at various offsets

54、 in the code. Constants were compared with known values and miscompares were transmitted along with relevant register information. </p><p>　　Registers – This test loaded each of four (0,1,2,3) banks of gener

55、al-purpose registers with either 0xAA (for banks 0 and 2) or 0x55 (for banks 1 and 3). The pattern was alternated in order to test the Program Status Word (PSW) special function register, which controls general-purpose r

56、egister bank selection. General-purpose register banks were then compared with their expected values. All miscompares were corrected and error information was transmitted.</p><p>　　Special Function Registers

57、 (SFR) – This test used learned static values of 12 out 21 available SFRs and then constantly compared the learned value with the current one. Miscompares were reloaded with learned value and error information was transm

58、itted. </p><p>　　Stack – This test performed arithmetic by pushing and popping operands on the stack. Unexpected results were attributed to errors on the stack or to the stack pointer itself and were transmi

59、tted with relevant register information.</p><p>　　VII. TEST METHODOLOGY </p><p>　　The DUT Computer booted by executing the instruction code located at address 0x0000. Initially, the device at th

60、is location was an EPROM previously loaded with "Boot/Serial Loader" code. This code initialized the DUT Computer and interface through a serial connection to the controlling computer, the "Test Controller

61、". The DUT Computer downloaded Test Code and put it into Program Code RAM (located on the Main Board of the DUT Computer). It then activated a circuit which simultaneously performed t</p><p>　　The Test

62、Control Computer always retained the ability to force the reset/remap function, regardless of the DUT Computer's functionality. Thus, if the test ran without a Single Event Functional Interrupt (SEFI) either the DUT

63、Computer itself or the Test Controller could have terminated the test and allowed the post-test functions to be executed. If a SEFI occurred, the Test Controller forced a reboot into Boot/Serial Loader code and then exec

64、uted the post-test functions.</p><p>　　During any test of the DUT, the DUT exercised a portion of its functionality (e.g., Register operations or Internal RAM check, or Timer operations) at the highest utili

65、zation possible, while making a minimal periodic report to the Test Control Computer to convey that the DUT Computer was still functional. If this report </p><p>　　ceased, the Test Controller knew that a SEF

66、I had occurred. This periodic data was called "telemetry". If the DUT encountered an error that was not interrupting the functionality (e.g., a data register miscompare) it sent a more lengthy report through th

67、e serial port describing that error, and continued with the test.</p><p>　　VIII. DISCUSSION</p><p>　　A. Single Event Latchup </p><p>　　The main argument for why latchup is not an is

68、sue for the CULPRiT devices is that the operating voltage of 0.5 volts should be below the holding voltage required for latchup to occur. In addition to this, the cell library used also incorporates the heavy dual guard-

69、barring scheme [4]. This scheme has been demonstrated multiple times to be very effective in rendering CMOS circuits completely immune to SEL up to test limits of 120 MeV-cm2/mg. This is true in circuits operating at 5,

70、3.3, and 2.5 V</p><p>　　B. Single Event Upset </p><p>　　The primary structure of the storage unit used in the CULPRiT devices is the Single Event Resistant Topology (SERT) [5]. Given the SERT ce

71、ll topology and a single upset node assumption, it is expected that the SERT cell will be completely immune to SEUs occurring internal to the memory cell itself. Obviously there are other things going on. The CULPRiT 805

72、1 results reported here are quite similar to some results </p><p>　　obtained with a CULPRiT CCSDS lossless compression chip (USES) [6]. The CULPRiT USES was synthesized using exactly the same tools and libra

73、ry as the CULPRiT 8051.</p><p>　　With the CULPRiT USES, the SEU cross section data [7] was taken as a function of frequency at two LET values, 37.6 and 58.5 MeV-cm2/mg. In both cases the data fit well to a l

74、inear model where cross section is proportional to clock. In the LET 37.6 case, the zero frequency intercept occurred essentially at the zero cross section point, indicating that virtually all of these SEUs are captured

75、SETs from the combinational logic. The LET 58.5 data indicated that the SET (frequency dependent) componen</p><p>　　The SET mitigation scheme used in the CULPRiT devices is based on the SERT cell's fault

76、 tolerant input property when redundant input data is provided to separate storage nodes. The idea is that the redundant input data is provided through a total duplication of combinational logic (referred to as “dual rai

77、l design”) such that a simple SET on one rail cannot produce an upset. Therefore, some other upset mechanism must be happening. It is possible that a single particle strike is placing an SET on</p><p>　　At t

78、his point, the theory for the CULPRiT SEU response is that at about an LET of 20, the energy deposition is sufficiently wide enough (and in the right locations) to produce an SET in both halves of the combinatorial logic

79、 streams. Increasing LET allows for more regions to be sensitive to this effect, yielding a larger cross section. Further, the second SEU mechanism that starts at an LET of about 40-60 has to do with when the charge coll

80、ection disturbance cloud gets large enough to effectivel</p><p>　　IX. SUMMARY </p><p>　　A detailed comparison of the SEE sensitivity of a HBD technology (CULPRiT) utilizing the 8051 microcontrol

81、ler as a test vehicle has been completed. This paper discusses the test methodology used and presents a comparison of the commercial versus CULPRiT technologies based on the data taken. The CULPRiT devices consistently s

82、how significantly higher threshold LETs and an immunity to latchup. In all but the memory test at the highest LETs, the cross section curves for all upset events is one to tw</p><p>　　This paper also demonst

83、rates the test methodology for quantifying the level of hardness designed into a HBD technology. By using the HBD technology in a real-world device structure (i.e., not just a test chip), and comparing results to equival

84、ent commercial devices, one can have confidence in the level of hardness that would be available from that HBD technology in any circuit application. </p><p>　　ACKNOWLEDGEMENTS </p><p>　　The aut

85、hors of this paper would like to acknowledge the sponsors of this work. These are the NASA Electronic Parts and Packaging Program (NEPP), NASA Flight Programs, and the Defense Threat Reduction Agency (DTRA).</p>&

86、lt;p>　　使用8051單片機驗證和測試單粒子效應(yīng)的加固工藝</p><p><b>　　摘要</b></p><p>　　隨著代工業(yè)務(wù)（抗輻射加固設(shè)計的芯片制造加工廠專門從事的一項業(yè)務(wù)）的減少，使用非專用代工業(yè)務(wù)的新技術(shù)逐步發(fā)展起來。在這篇論文中，我們將在空間環(huán)境中討論單粒子效應(yīng)（SEE）的驗證方法。課題包括需要測試的類型和設(shè)計覆蓋面（即他們是否需要驗證設(shè)計

87、庫的每個應(yīng)用程序？）。文章所提到的8051單片機核心是根據(jù)美國航天局的高級微電子研究所（ IAμE）的CMOS超低功耗輻射容錯技術(shù)（CULPRiT）設(shè)計的。它是評價兩個8051工業(yè)用設(shè)備單粒子效應(yīng)緩和技術(shù)的一項設(shè)計。</p><p><b>　　索引詞</b></p><p>　　單粒子效應(yīng)，加固工藝， 微控制器，輻射效應(yīng)。</p><p>&

88、lt;b>　　一 導言</b></p><p>　　美國航天局要在空間輻射環(huán)境中最低限度地使用資源條件下，不斷努力提供最好科學方法 [ 1,2 ] 。然而，擁有最先進的技術(shù)的工業(yè)用抗輻射加固微電子器件，幾代產(chǎn)品中都有相對局限性，所以美國航天局的這一任務(wù)很有挑戰(zhàn)性。本文所介紹的方法是使用加固微創(chuàng)設(shè)計技術(shù)的工業(yè)代工。這通常稱為加固工藝（HBD） 。</p><p>　　這種

89、使用設(shè)計程序庫和自動化設(shè)計工具設(shè)計的常規(guī)加固工藝器件可為美國宇航局提供一種解決方法，它能及時滿足嚴格的科學性能規(guī)格，具有成本低，和可靠性高的特點。</p><p>　　但是，仍然存在一個問題：常規(guī)輻射加固器件有許多和/或硅片輻射條件測試，加固工藝的驗證需要哪些類型的試驗？</p><p>　　二 加固工藝檢測設(shè)備的考慮</p><p>　　美國的測試技術(shù)是要使單個

90、器件通過如ASTM ，JEDEC的，和MIL - STD – 883等的標準和組織的測試。通常情況下使用的是TID（Co-60）和SEE（重離子和/或質(zhì)子）來驗證器件。那么，什么是HBD器件所獨有的驗證呢？</p><p>　　由于不采用“常規(guī)”工業(yè)現(xiàn)成（COTS）裝置或沒有固化的專用集成電路（ASIC），加固工藝的器件需要確定如何驗證設(shè)計程序庫而不是設(shè)備硬度。也就是說， 有了測試芯片，我們是不是就可以在未來器件

91、上使用相同的程序庫了？</p><p>　　試想，如果賣主A的設(shè)計的新的固化工藝程序庫可移植性可比賣主B和C的都好，那么A設(shè)計，測試的測試芯片就是可接受的了。9個月后，美國航天局飛行項目就會使用賣主A的程序庫設(shè)計了新器件進行組合了。這是否需要完成輻射條件測試？回答這個問題之前，先看一下其他的問題。</p><p>　　如何完整地測試芯片？所有程序庫元素來驗證每個單元是否有足夠的統(tǒng)計覆蓋？如

92、果美國航天局新的設(shè)計部分使用了設(shè)計程序庫或使用了沒有充分描述的部分，可能就需要全部測試了。當然，如果固化的部分工藝依靠一個進程的固有抗輻射硬度，也可以放棄一些測試（如SEL早先的樣本）。</p><p>　　另外，其他考慮因素還包括運作速度和工作電壓。例如，如果在電源電壓3.3V的條件下，用測試芯片靜態(tài)地測試單粒子效應(yīng)，所測得的數(shù)據(jù)在電源電壓2.5V 操作頻率100MHz的條件下是否適用？動態(tài)因素（即非靜態(tài)操作）

93、包括單粒子瞬變（SETs）的普及效果 。更高的頻率可能更關(guān)注這些。</p><p>　　需要考慮的因素是，設(shè)計程序庫，測試范圍，鑄造特點必須是已知的，并且深刻理解測試用途。如果所有這些因素都已經(jīng)具備或測試芯片已被驗證，那么測試就沒有必要了。美國航天局的電子零件封裝（ NEPP ）計劃是為了探討這些因素的類型。</p><p>　　三 用8051 單片機評估加固工藝</p>

94、<p>　　由于性能的不斷提高和功耗的不斷降低，微控制器在美國航天局和國防部的系統(tǒng)設(shè)計上的應(yīng)用正越來越多?，F(xiàn)在，美國航天局和國防部計劃正在不斷地改進固化工藝。微控制器是一個這樣的工具，正在深入量化抗輻射固化的改進。這些計劃的實例是Mission研究公司（ MRC ）與高級微電子研究所（這項研究的重點）所研制的8051 微控制器。在自然空間輻射環(huán)境中，由于這些固化工藝的使用，美國宇航局在航天飛行中系統(tǒng)中使用驗證技術(shù)成為必要。&l

95、t;/p><p>　　8051單片機是一個行業(yè)標準架構(gòu)，被廣泛接受和應(yīng)用，并作為一種開發(fā)工具。有許多工業(yè)供應(yīng)商，他們供應(yīng)這種控制器或把這種控制器集成到某種類型的系統(tǒng)芯片的結(jié)構(gòu)。醫(yī)學研究理事會和高級微電子研究所都選擇這個設(shè)備，但他們論證的是兩種截然不同固化工藝。醫(yī)學研究理事會的實例是使用時間鎖存，需要具體時間以確保單粒子效應(yīng)減少到最低限度。高級微電子研究所采用超低功耗，以及布局和建筑固化工藝的設(shè)計原則來實現(xiàn)其結(jié)果。這些

96、是與Aeroflex聯(lián)合技術(shù)微電子中心（ UTMC ）完全不同的方法 ，抗輻射固化的8051的工業(yè)供應(yīng)商，利用抗輻射固化進程研制自己的8051單片機。</p><p>　　一臺設(shè)備廣泛涉及的技術(shù)使得8051成為技術(shù)評價的理想載體這項工作的目標是從高級微電子研究所得到CMOS超低功耗輻射容錯進程的技術(shù)評價[ 3 ]。其他兩個過程--英特爾的8051商業(yè)設(shè)備標準和采用國家最先進的加工從達拉斯半導體版本—是這個進程的基

97、礎(chǔ)，。商業(yè)研究一 一比較了他們的成本效益，性能和可靠性。技術(shù)性能的評價是為測試微控制器開發(fā)硬件和軟件。完備進程中目的是優(yōu)化測試過程以盡可能獲得完整的評價。</p><p>　　這包括利用現(xiàn)有的硬件和在微控制器上運行的軟件對所有子處理器進行評價。這個進程還會使我們較完整地理解如何測試復(fù)雜的結(jié)構(gòu)，如微控制器，以及將來如何更有效地測試這些結(jié)構(gòu)。</p><p>　　四 測試裝置 這一試

98、驗的評價使用了三款器件。首先是美國航天局的設(shè)備，這是進行評估主要設(shè)備。其他兩個設(shè)備是兩種版本的商業(yè)8051 ，分別由英特爾公司和美國達拉斯半導體制造。</p><p>　　英特爾的設(shè)備是無存儲器型，這是經(jīng)典的8052 MCS - 51單片機電路版。他們工作環(huán)境是額定電壓+5伏，溫度范圍在0至70 °C，時鐘頻率為3.5兆赫至24兆赫。他們由英特爾P629.0 CHMOS III-E進程制造的。</

99、p><p>　　達拉斯半導體器件都很相似因為他們都是ROMless 8052單片機，但他們加強方式不同。他們的額定電壓從4.25至5.5,溫度在0到70 °C,時鐘頻率高達25兆赫。第二次全內(nèi)置串口，增設(shè)七個中斷，一個看門狗定時器，一個掉電復(fù)位，雙數(shù)據(jù)指針和變速外設(shè)訪問。此外，重新設(shè)計技術(shù)核心，最終使該機器周期縮短，從而得到有效的處理能力，這大約是2.5倍（快）比標準的8052器件。不同于器件工作所固有的功