msp430混合信號微控制器外文文獻(xiàn)及翻譯

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1、　　中文3570字　　本科畢業(yè)設(shè)計(jì)　　外文文獻(xiàn)及譯文　　文獻(xiàn)、資料題目：MPS430 Mixed Signal Microcontroller

2、;　　文獻(xiàn)、資料來源：期刊（著作、網(wǎng)絡(luò)等）　　文獻(xiàn)、資料發(fā)表（出版）日期：2005.3.25　　學(xué) 院：信息與電氣工程學(xué)院　　專業(yè)：通信工程　　班級：通信　　姓名： </b

3、>　　學(xué) 號： 　　指導(dǎo)教師： 　　翻譯日期： 　　外文文獻(xiàn)：　　　MSP430 MIXED SIG

4、NAL MICROCONTROLLER　　_ Low Supply-Voltage Range, 1.8 V . . . 3.6 V　　_ Ultralow-Power Consumption:　　? Active Mode: 330μA at 1 MHz, 2.2 V

5、　? Standby Mode: 1.1μA　　? Off Mode (RAM Retention): 0.1μA　　_ Five Power-Saving Modes　　_ Wake-Up From Standby Mode in less than 6μs　　_ 16

6、-Bit RISC Architecture, 125-ns Instruction Cycle Time　　_ Three-Channel Internal DMA　　_ 12-Bit A/D Converter With Internal　　Reference, Sample-and-Hold and Aut

7、oscan Feature　　_ Dual 12-Bit D/A Converters With Synchronization　　_ 16-Bit Timer_A With Three Capture/Compare Registers　　_ 16-Bit Timer_B With Three or Seven

8、 Capture/Compare-With-Shadow Registers　　_ On-Chip Comparator　　_ Serial Communication Interface (USART0), Functions as Asynchronous UART or Synchronous SPI or I2CTM Interface</

9、p>　　_ Serial Communication Interface (USART1), Functions as Asynchronous UART or Synchronous SPI Interface　　_ Supply Voltage Supervisor/Monitor With Programmable Level Detection</p&g

10、t;　　_ Brownout Detector　　_ Bootstrap Loader　　_ Serial Onboard Programming, No External Programming Voltage Needed　　Programmable Code Protection by

11、 Security　　Fuse　　_ Family Members Include:　　? MSP430F155:　　16KB+256B Flash Memory　　512B

12、 RAM　　? MSP430F156:　　24KB+256B Flash Memory　　1KB RAM　　? MSP430F157:　　32KB+256B Flash M

13、emory,　　1KB RAM　　? MSP430F167:　　32KB+256B Flash Memory,　　1KB RAM　　? MSP430F16

14、8:　　48KB+256B Flash Memory,　　2KB RAM　　? MSP430F169:　　60KB+256B Flash Memory,　　2KB RAM&l

15、t;/b>　　? MSP430F1610:　　32KB+256B Flash Memory　　5KB RAM　　? MSP430F1611:　　48KB+256B Flash Memor

16、y　　10KB RAM　　? MSP430F1612:　　55KB+256B Flash Memory　　5KB RAM　　_ Available in

17、64-Pin Quad Flat Pack (QFP) and 64-pin QFN (see Available Options)　　_ For Complete Module Descriptions, See the MSP430x1xx Family User’s Guide,　　Literature Number SLAU049</p&g

18、t;　　description　　The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications

19、. The architecture, combined with five low power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant ge

20、nerators that attribute to maximum code efficiency.　　The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6μs.　　The MSP430x15

21、x/16x/161x series are microcontroller configurations with two built-in 16-bit timers, a fast 12-bit　　A/D converter, dual 12-bit D/A converter, one or two universal serial synchronous/asynchronous<

22、/p>　　communication interfaces (USART), I2C, DMA, and 48 I/O pins. In addition, the MSP430x161x series offers　　extended RAM addressing for memory-intensive applications and large C-stack

23、 requirements. Typical applications include sensor systems, industrial control applications, hand-held meters, etc.　　MSP430F169 MIXED SIGNAL MICROCONTROLLER　　short-form descripti

24、on　　CPU　　The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are

25、 performed as register operations in　　conjunction with seven addressing modes for source operand and four addressing modes for　　destination operand.　　The CPU

26、 is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock.　　Four of the registers, R0 to R3, ar

27、e dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers.　　Peripherals are connected to the CPU using

28、 data, address, and control buses, and can be handled with all instructions.　　instruction set　　The instruction set consists of 51 instructions with three formats and seven addres

29、s modes. Each instruction can operate on word and byte data.　　operating modes　　The MSP430 has one active mode and five software selectable low-power modes of operation. An interr

30、upt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program.　　The following six operating mo

31、des can be configured by software:　　_ Active mode AM;　　? All clocks are active　　_ Low-power mode 0 (LPM0);　　? CPU is disabled

32、　　ACLK and SMCLK remain active. MCLK is disabled　　_ Low-power mode 1 (LPM1);　　? CPU is disabled　　ACLK and SMCLK remain active. MCLK is disabled<

33、/p>　　DCO’s dc-generator is disabled if DCO not used in active mode　　_ Low-power mode 2 (LPM2);　　? CPU is disabled　　MCLK and SMCLK are disabled&

34、lt;/p>　　DCO’s dc-generator remains enabled　　ACLK remains active　　_ Low-power mode 3 (LPM3);　　? CPU is disabled　　MCLK and S

35、MCLK are disabled　　DCO’s dc-generator is disabled　　ACLK remains active　　_ Low-power mode 4 (LPM4);　　? CPU is disabled<p&g

36、t;　　ACLK is disabled　　MCLK and SMCLK are disabled　　DCO’s dc-generator is disabled　　Crystal oscillator is stopped　　interrupt vector addre

37、sses　　The interrupt vectors and the power-up starting address are located in the address range 0FFFFh ? 0FFE0h.　　The vector contains the 16-bit address of the appropriate interru

38、pt-handler instruction sequence　　special function registers　　Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits not a

39、llocated to a functional purpose are not physically present in the device. This arrangement provides simple software access.　　interrupt enable 1 and 2　　WDTIE: Watchdog timer inte

40、rrupt enable. Inactive if watchdog mode is selected.　　Active if watchdog timer is configured as general-purpose timer.　　OFIE: Oscillator-fault-interrupt enable<p&g

41、t;　　NMIIE: Nonmaskable-interrupt enable　　ACCVIE: Flash memory access violation interrupt enable　　URXIE0: USART0: UART and SPI receive-interrupt enable　　UTXIE

42、0: USART0: UART and SPI transmit-interrupt enable　　URXIE1 : USART1: UART and SPI receive-interrupt enable　　UTXIE1 : USART1: UART and SPI transmit-interrupt enable<

43、p>　　URXIE1 and UTXIE1 are not present in MSP430x15x devices.　　interrupt flag register 1 and 2　　WDTIFG: Set on watchdog-timer overflow (in watchdog mode) or security key violat

44、ion　　Reset on VCC power-on, or a reset condition at the RST/NMI pin in reset mode　　OFIFG: Flag set on oscillator fault　　NMIIFG: Set via RST/NMI pin

45、　　URXIFG0: USART0: UART and SPI receive flag　　UTXIFG0: USART0: UART and SPI transmit flag　　URXIFG1 : USART1: UART and SPI receive flag　　UTXIFG1 :

46、USART1: UART and SPI transmit flag　　module enable registers 1 and 2　　URXE0: USART0: UART mode receive enable　　UTXE0: USART0: UART mode transmit enable</p&

47、gt;　　USPIE0: USART0: SPI mode transmit and receive enable　　URXE1 : USART1: UART mode receive enable　　UTXE1 : USART1: UART mode transmit enable　　US

48、PIE1 : USART1: SPI mode transmit and receive enable　　URXE1, UTXE1, and USPIE1 are not present in MSP430x15x devices.　　flash memory　　The flash memory can be p

49、rogrammed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:　　_ Flash

50、memory has n segments of main memory and two segments of information memory (A and B) of 128 bytes each. Each segment in main memory is 512 bytes in size.　　_ Segments 0 to n may be erased in one step

51、, or each segment may be individually erased.　　_ Segments A and B can be erased individually, or as a group with segments 0?n. Segments A and B are also called information memory.

52、;　　_ New devices may have some bytes programmed in the information memory (needed for test during manufacturing). The user should perform an erase of the information memory prior to the first use.　　p

53、eripherals　　Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, see the MSP430x1xx Family User’

54、s Guide, literature number SLAU049.　　DMA controller　　The DMA controller allows movement of data from one memory address to another without CPU intervention.

55、　For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consu

56、mption by allowing the CPU to remain in sleep mode without having to awaken to move data to or from a peripheral.　　oscillator and system clock　　The clock system in the MSP430x15x

57、 and MSP430x16x(x) family of devices is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal os

58、cillator. The basic clock module is designed to meet the requirements of both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 ?s. The basic c

59、lock module provides the f　　_ Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.　　_ Main clock (MCLK), the system clock used by the CPU.&l

60、t;/p>　　_ Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.　　brownout, supply voltage supervisor　　The brownout circuit is implemented to p

61、rovide the proper internal reset signal to the device during power on and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user selectable level and supports both suppl

62、y voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset). The CPU begins code execution after the brownout circuit releases the device reset. Ho

63、wever, VCC may not h　　digital I/O　　There are six 8-bit I/O ports implemented—ports P1 through P6:　　_ All individual I/O bits are independently programmable.&

64、lt;/p>　　_ Any combination of input, output, and interrupt conditions is possible.　　_ Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.<

65、;p>　　_ Read/write access to port-control registers is supported by all instructions.　　watchdog timer　　The primary function of the watchdog timer (WDT) module is to perform a c

66、ontrolled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an i

67、nterval timer and can generate interrupts at selected time intervals.　　hardware multiplier (MSP430x16x/161x Only)　　The multiplication operation is supported by a dedicated periph

68、eral module. The module performs 16_16, 16_8, 8_16, and 8_8 bit operations. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations. The re

69、sult of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are required.　　peripherals　　Periphe

70、rals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, see the MSP430x1xx Family User’s Guide, literature number SLAU049.</

71、p>　　DMA controller　　The DMA controller allows movement of data from one memory address to another without CPU intervention. 　　For example, the DMA controller can be

72、 used to move data from the ADC12 conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in

73、 sleep mode without having to awaken to move data to or from a peripheral.　　oscillator and system clock　　The clock system in the MSP430x15x and MSP430x16x(x) family of devices is

74、 supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock module is des

75、igned to meet the requirements of both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6μs. The basic clock module provides the fo&

76、lt;p>　　_ Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.　　_ Main clock (MCLK), the system clock used by the CPU.　　_ Sub-Main clock (

77、SMCLK), the sub-system clock used by the peripheral modules.　　brownout, supply voltage supervisor　　The brownout circuit is implemented to provide the proper internal reset signal

78、 to the device during power on and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision (the device is au

79、tomatically reset) and supply voltage monitoring (SVM, the device is not automatically reset).　　The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may no

80、t have ramped to VCC(min) at that time. The user must insure the default DCO settings are not changed until VCC reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).

81、　　digital I/O　　There are six 8-bit I/O ports implemented—ports P1 through P6:　　_ All individual I/O bits are independently programmable.　　_ Any com

82、bination of input, output, and interrupt conditions is possible.　　_ Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.　　_ Read/write access to

83、port-control registers is supported by all instructions.　　watchdog timer　　The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after

84、a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate

85、interrupts at selected time intervals.　　hardware multiplier (MSP430x16x/161x Only)　　The multiplication operation is supported by a dedicated peripheral module. The module perform

86、s 16_16, 16_8, 8_16, and 8_8 bit operations. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations. The result of an operation can be acc

87、essed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are　　required.　　USART0</p

88、>　　The MSP430x15x and the MSP430x16x(x) have one hardware universal synchronous/asynchronous receive transmit (USART0) peripheral module that is used for serial data communication. The USART supports synchr

89、onous SPI (3 or 4 pin), asynchronous UART and I2C communication protocols using double-buffered transmit and receive channels.　　The I2C support is compliant with the Philips I2C specification version

90、 2.1 and supports standard mode (up to 100 kbps) and fast mode (up to 400 kbps). In addition, 7-bit and 10-bit device addressing modes are supported, as well as master and slave modes. The USART0 also supports 16-bit-wid

91、e I2C data transfers and has two dedicated DMA channels to maximize bus throughput. Extensive interrupt capability is also given in the I2C mode.　　USART1 (MSP430x16x/161x Only)

92、The MSP430x16x(x) devices have a second hardware universal synchronous/asynchronous receive transmit (USART1) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin)

93、and asynchronous UART communication protocols, using double-buffered transmit and receive channels. With the exception of I2C support, operation of USART1 is identical to USART0.　　timer_A3&l

94、t;/b>　　Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interr

95、upt capabilities.　　Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.　　timer_B3 (MSP430x15x Only)<

96、p>　　Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities. Interr

97、upts may be generated from the counter on overflow conditions and from each of the capture/compare registers.　　timer_B7 (MSP430x16x/161x Only)　　Timer_B7 is a 16-bit timer/counter

98、 with seven capture/compare registers. Timer_B7 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities. Interrupts may be generated from the counter on

99、 overflow conditions and from each of the capture/compare registers.　　comparator_A　　The primary function of the comparator_A module is to support precision slope analog?to?digita

100、l conversions, battery?voltage supervision, and monitoring of external analog signals.　　ADC12　　The ADC12 module supports fast, 12-bit analog-to-digital convers

101、ions. The module implements a 12-bit SAR core, sample select control, reference generator and a 16 word conversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be conve

102、rted and stored without any CPU intervention.　　DAC12　　The DAC12 module is a 12-bit, R-ladder, voltage output DAC. The DAC12 may be used in 8- or 12-bit mode, a

103、nd may be used in conjunction with the DMA controller. When multiple DAC12 modules are present, they may be grouped together for synchronous operation.　　中文譯文：

104、　MSP430混合信號微控制器　　● 低供電電壓范圍：1.8V…3.6V　　● 超低功耗：　?。顒幽Ｊ剑?MHz，2.2V 時(shí)為280μA　?。却Ｊ剑?.6μA　?。P(guān)閉模式（RAM 保

105、持）：0.1μA　　● 五種省電模式　　● 6μS 內(nèi)從等待狀態(tài)喚醒　　● 16 位精簡指令結(jié)構(gòu)，125 納秒指令時(shí)間周期　　● 三個(gè)內(nèi)部 DMA 通道　　● 具有內(nèi)部參考電平、采樣保持和自動

106、掃描特性的 12 位A/D 轉(zhuǎn)換器　　● 同步的雙 12 位D/A 轉(zhuǎn)換器　　● 帶有三個(gè)捕捉/比較寄存器的16 位定時(shí)器A　　● 帶有三個(gè)或七個(gè)捕捉/比較影子寄存器的16 位定時(shí)器B　　● 片內(nèi)集成比較器&l

107、t;p>　　● 串行通訊接口（USART1），具有異步UART 或者同步SPI 接口的功能　　● 串行通訊接口（USART0），具有異步UART 或者同步SPI 或者I2C 接口　　● 具有可編程電平檢測的供電電壓管理器/監(jiān)視器　　● 欠電壓檢測器

108、　　● 串行在線編程，無需外部編程電壓，可編程的安全熔絲代碼保護(hù)　　● Bootstrap Loader　　● 器件系列包括：　　－MSP430F155:　　16KB+256B flash 存儲器

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