SoC高層建模與性能優(yōu)化技術(shù)研究.pdf

1、東南大學(xué)博士學(xué)位論文SoC高層建模與性能優(yōu)化技術(shù)研究姓名：張宇申請學(xué)位級別：博士專業(yè)：微電子學(xué)與固體電子學(xué)指導(dǎo)教師：時龍興20070914AbstractAbstractwilhtheh嵋嬲eofrequestsoftimetomarketandperformanceforSoCproductsbymatkegtraditionaldesignmethodforASICcannotsarisfytherequestsMeanwhile，

2、theimprovementofperformancerestrictedwithcostandpowerisbecomingthenewchallengeofdesignSo，thedesignmethodbasedonSoChi吐abslr3EtlevelmodelbecomesallimportantmeamforSW／HWcodesignAndastoperformanceoptimizationdesignmemorysubs

3、ystemisoneofkeybottlenecksofperformance，powerandcostforSoCThepaperbuildstheSoCmodelusingmixedmodelingmethodandperformanceevaluationplatformformemorysubsystemandthengivestheoptimizationdesignofmemorysubsystemfortwo32bitse

4、mbeddedmicroprocessorsTheworksofthepaperinclude：nbuildstheSoChighabstractlevelmodelforSEP3203embeddedmicroprocessorbasedollARMcoreInordertoexecutetheinstructionandemulatethebehaviorofproce$soracctwatelyandquicldy，theinst

5、ructionsetsimulator(ISS)ofARM，namedARMulatorisemployedToguaranteethemodelsrealityofhardwarebusandmemorysubsystemarerealizedbyuseofSystemC1kmemoryincludesexternalmemorycontrollerSDRAM，SPMandCAcHE2)Theperformanceevaluation

6、platformformemorysubsystemisbuiltonSoCmodelandinstructiondataandstackareselectedasevaluationobjectsThroughtheanalysisofobjects，theSDRAMcontrollerofSEP3203embeddedmicroprocessorisoptimizedandreforme山T1“simulationresultssh

7、owlhereformedcontrollerreducesthelatencyofacxcsstoSDRAMtoagreatextentAndthentheScratchPadMemoryinSEP3203embeddedmicroprocessorisanalyze正111einstructionSPMthedataSPMandstackSPMmin們dllcedinthepapertooptimizetheinstruction，

8、dataandstackseparatelyTheexperimentsshowthattheSPMcanimprovethesystemperformancegreatlyunderalittleofcapacity3、Toimprovetheperforma∞eofSOCmemorysubsystemfarthertheCACHEisemployedThepaperfirstsetsupthedesignparameterexplo

9、rationtoolsforCACHEandthenuseSPMteducethemissrateofCACHESPMismainlytostorethestackanddataconsideringtheaccessconflictsbe鯫，僦instructionanddata／stackandtherestrictionofchipareaThcdesignmethodofCACHEwithSPMgivesthedesigndir

10、ectionformemorysubsystemarchitectureofSEP3221embeddedmicroprocessorTheSoCmodelbuiltinthepaperc姐reachthehighprecision1|pto98％whilethespeedofverificationismorethan1000timescomparedwith曲ecircuitR豇verificationAndthenareforme

11、dSDRAMcontrollerisdesignedtoreducetheaccesslatencyto60％ForoptimizedsPMtheinstructionSPMcove培60％insmlctinnaccessby9KbytesthedataSPMcovers96％dataaccessbyIKb”esandstackSPMcoveys91％stack∽cessbyO5勛ytes，F(xiàn)ormoreoptimization，CAc

12、HEwithsPMisemployedAsalldataandstackarestoredinSPM，themissrateofCAC胍isdecreasedby62％andthewholechinexecutingperformanceisadvancedby183％comparedwithusingCAC腿onlyKeywords：Systemon—aChip，HighlevelSimulationModelSystemC，Perf