基于數(shù)據(jù)通路各運算部件的通用數(shù)字信號處理器設(shè)計與實現(xiàn).pdf

1、Y779858分類號：密級：單位代碼：10422學(xué)：=：⑧∥▲東’，番碩士學(xué)位論文ShandongUniversityJaster’sThesiS論文題目：基于數(shù)據(jù)通路各運算部件的通用數(shù)字信號處理器設(shè)計與實現(xiàn)作者姓名姚軍專業(yè)微電子學(xué)與固體電子學(xué)指導(dǎo)教師姓名孥業(yè)技術(shù)職務(wù)林兆軍教授陳杰研究員2005年3月20日山東大學(xué)碩士學(xué)位論文ABSTRACTWiththerapiddevelopmentofmicroelectronics，digita

2、lsignalprocessingtechnologiesandcomputertechnologies，DigitalSignalProcessoremergedAsthetechnologymakesprogressrapidlyinmicroelcctronics，thefeaturesizehasbeenreducedbelow018um，even013umandthetechnologyoffeaturesizeO09umha

3、sbeenpopularBased0ntheimprovementoftechnology，themicroprocessorwhichrepresentstheleveloftheintegratedcircuitisupdatedconstantlyandbecomesstrongerandstronger，soasthedevelopmentofDSPA16bitfixedpointDSPwithhighperformanceis

4、introducedThefocusofthisthesisistodesignandimplementthecomputationalunitbasedondatapathofDSPAsix—levelpipeliningisusedwhendesigningthearchitecture，whichpredigeststhecontrolofpipelinewithoutlossofperformanceThebusarchitec

5、tureaccordswithModifiedHarvardarchitecturewhichcanprovideenoughdatarateforcomputingunitsTheMACunitoftheDSPisfastenoughtoaccomplishamultiplicationandanaccumulationTheparalleltechnologyisusedsothattheDSPcandoacomputationan

6、dgettwooprandsfromonchipmemoryinasinglecycleZero—overheadloopisimplementedanddelaybranchisrealizedtomakethepipelinemoreefficientBehavioralmodelsaremadefordatapathandcontrolpathTofunctionasareferenceonprojectscheduling，ta

7、skpartitioningforfuturedesignerasetofmethodofgeneralpurposeDSPdesignandimplementationissummarizedinthisthesisThestrategyofverificationandchiptestarealsomentionedKeywords：digitalsignalprocessing(DSP)，designmethod，multiply