基于fpga的數(shù)字鐘設(shè)計(jì)

1、河北經(jīng)貿(mào)大學(xué)畢業(yè)論文 河北經(jīng)貿(mào)大學(xué)畢業(yè)論文基于 基于 FPGA 的數(shù)字鐘設(shè)計(jì) 的數(shù)字鐘設(shè)計(jì)AbstractThe FPGA technology in the electronic system design field, this design is becoming more and more popular. VerilogHDL mainly uses in the FPGA platform design language o

2、f electronic digital clock, it is one of the timing cycle for 365 days, show when full scale for 23, coupled with 59 seconds to 59 points on the time of function, display full scale for December 31ston the date of functi

3、on, it also has reset function and alarm clock function. General program with different functions by several each unit module program into joining together, including points frequency program module, time counting and Se

4、ttings when program modules, decode show program modules and integral point to announce the module. And use QuartusII software simulation, circuit waveform validated. download to EDA Experimental box. This design uses a

5、top-down with EP1C3T144, mixed input methods (diagram input - top level file links and VerilogHDL language input - each module design program) to implement a digital clock design, download and test.Keywords FPGA Chip;