外文文獻(xiàn)翻譯----32kx16閃存16位語(yǔ)音微控制器

1、<p>　　32kx16閃存16位語(yǔ)音微控制器</p><p><b>　　1 總述 </b></p><p>　　SPCE061A 是繼μ’nSP(TM)系列產(chǎn)品 SPCE500A 等之后凌陽(yáng)科技推出的又一個(gè)16位結(jié)構(gòu)的微控制器。與SPCE500A不同的是，在存儲(chǔ)器資源方面考慮到用戶的較少資源的需求以及便于程序調(diào)試等功能，SPCE061A里只內(nèi)嵌32K字

2、的閃存 FLASH ROM。較高的處理速度使μ’nSP(TM)能夠非常容易地、快速地處理復(fù)雜的數(shù)字信號(hào)。因此，與SPCE500A相同，以μ’nSP(TM)為核心的SPCE061A微控制器也適用在數(shù)字語(yǔ)音識(shí)別應(yīng)用領(lǐng)域。 </p><p>　　SPCE061A在3.0V-3.6V工作電壓范圍內(nèi)的工作速度范圍為 0.32MHz-49.152MHz，較高的工作速度使其應(yīng)用領(lǐng)域更加拓寬。2K 字 SRAM 和 32K 字閃

3、存 ROM 僅占一頁(yè)存儲(chǔ)空間，32 位可編程的多功能 I/O 端口；兩個(gè) 16 位定時(shí)器/計(jì)數(shù)器；32768Hz實(shí)時(shí)時(shí)鐘；低電壓復(fù)位/監(jiān)測(cè)功能；8通道10位模-數(shù)轉(zhuǎn)換輸入功能并具有內(nèi)置自動(dòng)增益控制功能的麥克風(fēng)輸入方式；雙通道10位 DAC方式的音頻輸出功能 。</p><p><b>　　2 性能 </b></p><p>　　* 16位μ’nSP(TM)微處理器

4、 </p><p>　　* CPU時(shí)鐘：0.32MHz-49.152MHz </p><p>　　* 工作電壓：3.0V - 3.6V </p><p>　　* 內(nèi)置2K字SRAM</p><p>　　* 內(nèi)置32K閃存ROM </p><p>　　* 可編程音頻處理</p><p>

5、;<b>　　* 晶體振蕩器</b></p><p>　　* 系統(tǒng)處于備用狀態(tài)下(時(shí)鐘處于停止?fàn)顟B(tài))，耗電小于2μA@3.6V </p><p>　　* 2個(gè)16位可編程定時(shí)器/計(jì)數(shù)器(可自動(dòng)預(yù)置初始計(jì)數(shù)值) </p><p>　　* 2個(gè)10位DAC(數(shù)-模轉(zhuǎn)換)輸出通道 </p><p>　　* 32位通用

6、可編程輸入/輸出端口</p><p>　　* 14個(gè)中斷源可來(lái)自定時(shí)器A / B，時(shí)基，2 個(gè)外部時(shí)鐘源輸入，鍵喚醒</p><p>　　* 具備觸鍵喚醒的功能</p><p>　　* 使用凌陽(yáng)音頻編碼 SACM_S200 方式(2.0K 位/秒) </p><p>　　* 鎖相環(huán)PLL振蕩器提供系統(tǒng)時(shí)鐘信號(hào) </p>

7、<p>　　* 32768Hz實(shí)時(shí)時(shí)鐘 </p><p>　　* 8通道10位電壓模-數(shù)轉(zhuǎn)換器(ADC)和單通道聲音模-數(shù)轉(zhuǎn)換器聲音模-數(shù)轉(zhuǎn)換器輸入</p><p>　　* 通道內(nèi)置麥克風(fēng)放大器和自動(dòng)增益控制(AGC)功能 </p><p>　　* 具備串行設(shè)備接口</p><p>　　* 低電壓復(fù)位(LVR)功能和低電壓

8、監(jiān)測(cè)(LVD)功能</p><p>　　* 保護(hù)代碼安全讀與寫的功能</p><p><b>　　3 應(yīng)用領(lǐng)域 </b></p><p>　　* 語(yǔ)音識(shí)別類產(chǎn)品 </p><p>　　* 智能語(yǔ)音交互式玩具 </p><p>　　* 高級(jí)亦教亦樂(lè)類玩具 </p><p

9、>　　* 兒童電子故事書(shū)類產(chǎn)品 </p><p>　　* 通用語(yǔ)音合成器類產(chǎn)品 </p><p>　　* 需較長(zhǎng)語(yǔ)音持續(xù)時(shí)間類產(chǎn)品 </p><p>　　* 復(fù)讀機(jī)相關(guān)產(chǎn)品</p><p><b>　　4 功能描述 </b></p><p><b>　　4.1 CPU

10、</b></p><p>　　SPCE061A 配備了凌陽(yáng)科技開(kāi)發(fā)的最新的16位微處理器μ’nSP(TM)。它內(nèi)含有8個(gè)寄存器：4個(gè)通用寄存器R1-R4，1個(gè)程序計(jì)數(shù)器PC，1個(gè)堆棧指針SP，1個(gè)基址指針BP和1 個(gè)段寄存器 SR。通用寄存器 R3 和 R4 結(jié)合形成一個(gè) 32位寄存器MR，MR可被用作乘法運(yùn)算和內(nèi)積運(yùn)算的目標(biāo)寄存器。此外，SPCE061A 有3 個(gè)FIQ中斷和14個(gè)IRQ中斷，并且?guī)?/p>

11、有一個(gè)由指令BREAK控制的軟中斷。μ’nSP(TM)不僅可以進(jìn)行加、減等基本算術(shù)運(yùn)算和邏輯運(yùn)算，還可以完成用于數(shù)字信號(hào)處理的乘法運(yùn)算和內(nèi)積運(yùn)算。 </p><p><b>　　4.2 存儲(chǔ)器 </b></p><p>　　4.2.1. RAM </p><p>　　SPCE061A 擁有 2K 字的 SRAM(包括堆棧區(qū))，其地址范圍從#00

12、00到#07FF。 用兩個(gè)時(shí)鐘周期進(jìn)行訪問(wèn)。</p><p>　　4.2.2 閃存（Flash）ROM </p><p>　　閃存（Flash）ROM（＃008000-＃00FFFF）是一種以兩個(gè)CPU時(shí)鐘周期存取速度的高速內(nèi)存。閃存擦寫功能必須使用IDE工具。</p><p>　　4.3 時(shí)鐘（鎖相環(huán)振蕩器，系統(tǒng)時(shí)鐘，實(shí)時(shí)時(shí)鐘） </p><

13、p>　　4.3.1 鎖相環(huán)(PLL，Phase Lock Loop)振蕩器 </p><p>　　PLL 的作用是為系統(tǒng)提供一個(gè)實(shí)時(shí)時(shí)鐘的基頻(32768Hz)，然后將基頻進(jìn)行倍頻，調(diào)整至 49.152MHz、40.96MHz、32.768MHz、24.576MHz或 20.480MHz。系統(tǒng)</p><p>　　默認(rèn)的PLL自激振蕩頻率為24.576MHz。 </p>

14、<p><b>　　4.3.2 時(shí)鐘 </b></p><p>　　(1)系統(tǒng)時(shí)鐘 一般來(lái)說(shuō)，系統(tǒng)時(shí)鐘的信號(hào)源為 PLL 振蕩器。系統(tǒng)時(shí)鐘頻率(Fosc)和 CPU 時(shí)鐘頻率 (CPUCLK) 可通過(guò)對(duì)P_SystemClock(寫)(#7013H)單元編程來(lái)控制。默認(rèn)的Fosc、CPUCLK分別為24.576MHz 和Fosc/8。用戶可以通過(guò)對(duì) P_SystemClock

15、單元編程完成對(duì)系統(tǒng)時(shí)鐘和 CPU 時(shí)鐘頻率的定義。當(dāng)系統(tǒng)被喚醒后最初時(shí)刻的CPUCLK頻率亦為Fosc/8，隨后逐漸被調(diào)整到用戶設(shè)定的 CPUCLK 頻率。這樣，可避免系統(tǒng)在喚醒初始時(shí)刻讀ROM出現(xiàn)錯(cuò)誤。 </p><p>　　(2)實(shí)時(shí)時(shí)鐘（32768Hz） 32768Hz實(shí)時(shí)時(shí)鐘通常用于鐘表、實(shí)時(shí)時(shí)鐘延時(shí)以及其它與時(shí)間相關(guān)類產(chǎn)品。SPCE061A 通過(guò)對(duì) 32768Hz 實(shí)時(shí)時(shí)鐘源分頻而提供了多種實(shí)時(shí)時(shí)鐘中

16、斷源。例如，用作喚醒源的中斷源 IRQ5_2Hz，表示系統(tǒng)每隔 0.5 秒被喚醒一次，由此可作為精確的計(jì)時(shí)基準(zhǔn)?！?。此外， SPCE061A支持32768Hz振蕩器在正常模式和自動(dòng)省電模式。在正常模式下，32768Hz振蕩器始終運(yùn)行在最高的功率消耗。自動(dòng)省電模式，但是，在正常模式下運(yùn)行的第一個(gè)7.5秒變化回到省電模式以降低功耗。 </p><p>　　4.4 節(jié)電模式 </p><p>

17、;　　SPCE061A可設(shè)置節(jié)電的備用模式以達(dá)到節(jié)能的目的。要進(jìn)入待命工作模式，首先應(yīng)將所需的鍵喚醒口IOA[7-0]設(shè)為輸入端口。在進(jìn)入待命工作模式前，通過(guò)讀P_IOA_Latch 單元來(lái)激活I(lǐng)OA[7-0]口的喚醒功能，或者允許作為喚醒源的中斷源中斷請(qǐng)求的響應(yīng)；然后通過(guò)寫入P_SystemClock單元一個(gè)CPUClk STOP 控制字（CPU 睡眠信號(hào)），以停止 CPUClk 工作，進(jìn)入‘睡眠’狀態(tài)。P_SystemClock單元

18、還可用來(lái)編程設(shè)置在CPU進(jìn)入‘睡眠’時(shí)是禁止/允許32768Hz實(shí)時(shí)時(shí)鐘的工作。在待命模式下，RAM和I/O端口的狀態(tài)都將維持進(jìn)入‘睡眠’前的各個(gè)狀態(tài)，直到產(chǎn)生‘喚醒’信號(hào)。SPCE061A的喚醒源包括鍵喚醒 IOA[7-0]端口以及各中斷源（IRQ0 - IRQ6）。當(dāng) SPCE061A 的 CPU 被喚醒后，會(huì)繼續(xù)執(zhí)行程序指令。 程序員也可以啟用或禁用32768Hz振蕩時(shí)的CPU是否在待機(jī)模式。</p><p&g

19、t;　　4.5 低電壓監(jiān)測(cè)和低電壓復(fù)位</p><p>　　4.5.1 低電壓監(jiān)測(cè)</p><p>　　有兩個(gè)LVD可以被選定：2.9V和3.3V。這兩個(gè)級(jí)別可以通過(guò)Port_LVD_Ctrl編程（W） 。例如，假設(shè)LVD給予的2.9V。當(dāng)電壓降到2.9V以下 ，B15的Port_LVD_Ctrl讀出的是為高。在這樣的狀態(tài)，可以設(shè)計(jì)程序?qū)@一條件作出反應(yīng)。</p><

20、p>　　4.5.2 低電壓復(fù)位 </p><p>　　除了LVD，該SPCE061A的另一個(gè)重要功能，低電壓復(fù)位（ LVR ） 。與LVR功能，復(fù)位信號(hào)產(chǎn)生時(shí)重置系統(tǒng)的工作電壓低于2.3V連續(xù)10 CPU時(shí)鐘周期.如果沒(méi)有 LVR ，中央處理器變得不穩(wěn)定和發(fā)生故障時(shí)，工作電壓低于2.3V 。當(dāng)電壓低于2.3V ，該LVR將重置所有功能到初始操作狀態(tài)（穩(wěn)定） 。</p><p><

21、;b>　　4.6 中斷</b></p><p>　　SPCE061A 具有兩種中斷方式：快速中斷請(qǐng)求FIQ(快速中斷請(qǐng)求)中斷和中斷請(qǐng)求 IRQ(中斷請(qǐng)求)中斷。中斷控制器可處理3種FIQ中斷和14種IRQ中斷，以及一個(gè)由指令BREAK控制的軟中斷。 相比之下，F(xiàn)IQ中斷的優(yōu)先級(jí)較高而IRQ 中斷的優(yōu)先級(jí)較低。也就是說(shuō)，F(xiàn)IQ中斷可以中斷IRQ 中斷服務(wù)子程序的執(zhí)行，而CPU執(zhí)行相應(yīng)的FIQ中斷

22、服務(wù)子程序的過(guò)程不能被任何中斷源的中斷請(qǐng)求中斷。</p><p>　　4.7 輸入/輸出端口 </p><p>　　兩個(gè)I/O端口是建立在SPCE061A，端口A和端口B。端口A是一個(gè)普通的I/O ，有編程喚醒功能。除了定期的IO功能，端口B還可以在某些引腳執(zhí)行一些特殊的功能。假設(shè)正在運(yùn)行的工作電壓在3.6V（電源）和VDDIO （I / O電源的 ）之間 ，從3.6V之間（電源）至5.5

23、V 。在這種條件下，在I / O墊能夠從0V通過(guò)VDDIO 。雖然IOB13和IOB14建議在<=3.6V之間 的待機(jī)模式下操作，然而這兩個(gè)端口間依然有電流泄漏。下面的圖表是一個(gè)I / O示意圖。</p><p>　　雖然數(shù)據(jù)能經(jīng)過(guò)數(shù)據(jù)端口和端口緩沖器被寫入相同的寄存器, 但是，他們能從不同的地方、緩沖(R)和數(shù)據(jù) (R)被讀取。端口A[7:0] 是主要的喚醒端口。為了要激活主要的喚醒功能, 在 PORT_

24、IOA_Latch 上的數(shù)據(jù),而且使主要 喚醒 功能能夠。當(dāng)端口A在不同于其它端口狀態(tài)時(shí)被喚醒。除了作為一個(gè)平常的輸入／輸出功能之外,端口B還具有一些特別的功能。 </p><p>　　4.8 定時(shí)器/計(jì)數(shù)器</p><p>　　SPCE061A提供了兩個(gè)16位的定時(shí)器/計(jì)數(shù)器：TimerA和TimerB 。 為通用計(jì)數(shù)器； 為多功能計(jì)數(shù)器。TimerA TimerB的時(shí)鐘源由時(shí)鐘源

25、 和時(shí)鐘源 進(jìn)行“與”操作而TimerB的時(shí)鐘源僅為時(shí)鐘源A。定時(shí)器發(fā)生溢出后會(huì)產(chǎn)生一個(gè)溢出信號(hào)(TAOUT/TBOUT)。一方面，它會(huì)作為定時(shí)器中斷信號(hào)傳輸給CPU中斷系統(tǒng)；另一方面，它又會(huì)作為4位計(jì)數(shù)器計(jì)數(shù)的時(shí)鐘源信號(hào)，輸出一個(gè)具有 4 位可調(diào)的脈寬調(diào)制占空比輸出信號(hào) 或 分別從 和APWMO BPWMO( IOB8 IOB9 輸出)，用來(lái)控制馬達(dá)或其它一些設(shè)備的速度。此外，定時(shí)器溢出信號(hào)還可以用于觸發(fā) 輸入的自動(dòng)轉(zhuǎn)換過(guò)程ADC和D

26、AC輸出的數(shù)據(jù)鎖存。 </p><p>　　向定時(shí)器的讀寫單元或P_TimerA_Data(#700AH)P_TimerB_Data(讀/寫)(#700CH)單元寫入一個(gè)計(jì)數(shù)值N后，選擇一個(gè)合適的時(shí)鐘源，定時(shí)器/計(jì)數(shù)器將在所選的時(shí)鐘頻率下開(kāi)始以遞增方式計(jì)數(shù)N，N+1，N+2，…0xFFFE，0xFFFF。當(dāng)計(jì)數(shù)達(dá)到0xFFFF后，定時(shí)器/計(jì)數(shù)器溢出，產(chǎn)生中斷請(qǐng)求信號(hào)，被CPU 響應(yīng)后送入中斷控制器進(jìn)行處理。同

27、時(shí)，N 值將被重新載入定時(shí)器/計(jì)數(shù)器并重新開(kāi)始計(jì)數(shù)。 在TimerA內(nèi)，時(shí)鐘源A是一個(gè)高頻時(shí)鐘源，時(shí)鐘源B是一個(gè)低頻時(shí)鐘源。時(shí)鐘源 A和時(shí)鐘源 B 的組合，為TimerA 提供出多種計(jì)數(shù)速度。若以ClkA作為門控信號(hào)，‘1’表示允許時(shí)鐘源B信號(hào)通過(guò)，而‘0’則表示禁止時(shí)鐘源B信號(hào)通過(guò)而停止TimerA的計(jì)數(shù)。例如，如果時(shí)鐘源A 為“1”，TimerA時(shí)鐘頻率將取決于時(shí)鐘源B；如果時(shí)鐘源A為“0”，將停止TimerA的計(jì)數(shù)。EXT1和EX

28、T2為外部時(shí)鐘源。多種時(shí)鐘期間能產(chǎn)生并且從 IOB8(APWMO) 和 IOB9(BPWMO) 輸出。 </p><p>　　下圖為一個(gè)3/16的脈寬調(diào)制占空比輸出信號(hào)產(chǎn)生過(guò)程的時(shí)序。APWMO波形是通過(guò)寫入P_TimeA_Ctrl 單元的B9-B6選擇一個(gè)脈寬數(shù)（以計(jì)數(shù)溢出周期數(shù)定義）產(chǎn)生出來(lái)的，即每16個(gè)計(jì)數(shù)溢出周期將產(chǎn)生一個(gè)由上述單元定義的脈寬。此類PWM信號(hào)可以用于控制馬達(dá)及其它設(shè)備的速度。</p&

29、gt;<p>　　一般來(lái)說(shuō)，時(shí)鐘源A為高速時(shí)鐘源，時(shí)鐘源B來(lái)自實(shí)時(shí)時(shí)鐘32678Hz 系統(tǒng)。因此，時(shí)鐘源B能用于一個(gè)精確的時(shí)間計(jì)數(shù)器。例如，2Hz 時(shí)鐘信號(hào)可用于實(shí)時(shí)時(shí)間計(jì)數(shù)。 </p><p>　　一般來(lái)說(shuō)，時(shí)鐘源 A 和 C 是快速的時(shí)鐘來(lái)源，而且源 B 來(lái)自 RTC 系統(tǒng) (32768個(gè)赫茲) 。因此，時(shí)鐘源 B能用于一個(gè)精確的時(shí)間計(jì)數(shù)器.舉例來(lái)說(shuō)，2Hz 時(shí)鐘信號(hào)可用于實(shí)時(shí)時(shí)間計(jì)數(shù)。<

30、/p><p>　　4.8.1 時(shí)基 </p><p>　　時(shí)間基準(zhǔn)信號(hào)，簡(jiǎn)稱時(shí)基信號(hào)，來(lái)自于32768Hz實(shí)時(shí)時(shí)鐘，通過(guò)頻率選擇組合而成。時(shí)基信號(hào)發(fā)生器的2個(gè)選頻邏輯TMB1和TMB2為TimerA的時(shí)鐘源B提供各種頻率選擇</p><p>　　信號(hào)并為中斷系統(tǒng)提供中斷源(IRQ6)信號(hào)。此外，時(shí)基信號(hào)發(fā)生器還可以直接生成2Hz、4Hz、1024Hz、2048Hz以及

31、4096Hz的時(shí)基信號(hào)，為中斷系統(tǒng)提供各種實(shí)時(shí)中斷源(IRQ4和IRQ5)信號(hào)。 </p><p>　　4.9 睡眠、喚醒與看門狗 </p><p>　　4.9.1 睡眠與喚醒 </p><p>　　(1) 睡眠：IC在上電復(fù)位開(kāi)始工作，直到接收到睡眠信號(hào)后，才關(guān)閉系統(tǒng)時(shí)鐘(PLL振蕩器)，進(jìn)入睡眠狀態(tài)。系統(tǒng)進(jìn)入睡眠狀態(tài)后，程序計(jì)數(shù)器(PC)會(huì)停在程序的下一條

32、指令計(jì)數(shù)上，當(dāng)有任一喚醒事件發(fā)生后開(kāi)始由此繼續(xù)執(zhí)行程序。 </p><p>　　(2) 喚醒：若要將系統(tǒng)從睡眠狀態(tài)喚醒，需要有喚醒源提供一個(gè)喚醒信號(hào)來(lái)啟動(dòng)系統(tǒng)時(shí)鐘。IRQ中斷請(qǐng)求信號(hào)引導(dǎo)CPU 完成喚醒過(guò)程并將系統(tǒng)初始化。</p><p>　　IRQ3_KEY為觸鍵喚醒源(IOA7-0)，其它中斷源(FIQ、IRQ1-IRQ6 及UART IRQ)都可以作為喚醒源。</p>

33、<p>　　4.9.2 看門狗</p><p>　　看門狗的目的是檢測(cè)系統(tǒng)是否正常操作 。在一個(gè)特定的時(shí)期之內(nèi)，看門狗一定要被清除。如果看門狗沒(méi)被清除的，處理器會(huì)認(rèn)為系統(tǒng)一直在一種不正常的情況運(yùn)行。 結(jié)果，處理器將會(huì)重新把系統(tǒng)返回到初始狀態(tài)而且會(huì)再次重新運(yùn)行程序?？撮T狗功能能在選項(xiàng)中移除。在 SPCE061 A ，清除的周期是0.75 秒。如果看門狗在每 0.75 秒之內(nèi)被清除的，系統(tǒng)將不會(huì)再重新運(yùn)行

34、。為了清除看門狗,只用是寫 "xxxx xxxx xxxx xx 01B" 給 Port_Watchdog_Clear(W) 。 寫到給看門狗清除的 Port_Watchdog_Clear(W) 的內(nèi)容一定完全地是相同于在上面列舉(xxxx xxxx xxxx xx 01B).其他有用的價(jià)值會(huì)在用 Port_Watchdog_Clear(W)給看門狗清除,系統(tǒng)重新啟動(dòng)時(shí)被結(jié)束使用。如果32768 赫茲被使能,在睡眠模

35、式下，看門狗功能依然能夠被使用。 </p><p>　　4.10 模數(shù)轉(zhuǎn)換器與數(shù)/模轉(zhuǎn)換器 </p><p>　　SPCE061 A 有八個(gè)模-數(shù)轉(zhuǎn)換器通道.模-數(shù)轉(zhuǎn)換的功能將模擬信號(hào)轉(zhuǎn)換成數(shù)字信號(hào), 舉例來(lái)說(shuō) 電壓轉(zhuǎn)換成數(shù)字信號(hào)。其中7個(gè)通道用于將模擬量信號(hào) (例如電壓信號(hào)) 轉(zhuǎn)換為數(shù)字量信號(hào), 可以直接通過(guò)引線(IOA[0-6])輸入。另外有一個(gè)通道只作為語(yǔ)音輸入通道，通過(guò)內(nèi)置有

36、自動(dòng)增益控制放大器的麥克風(fēng)通道(MIC_IN)輸入。另外一個(gè)獨(dú)立的電阻可以被用來(lái)適應(yīng) 麥克風(fēng)的增益和AGC操作的時(shí)間 .AD 需要在轉(zhuǎn)變之前選擇線性源。 </p><p>　　4.11 串行設(shè)備接口 </p><p>　　串行輸入輸出端口SIO提供了一個(gè)1位的串行接口，用于與其它設(shè)備進(jìn)行數(shù)據(jù)通訊。在SPCE061A內(nèi)通過(guò)IOB0和IOB1這2個(gè)端口實(shí)現(xiàn)與設(shè)備進(jìn)行串行數(shù)據(jù)交換功能。 <

37、;/p><p>　　4.12 UART </p><p>　　UART 模塊提供了一個(gè)全雙工標(biāo)準(zhǔn)接口，用于完成SPCE061A 與外設(shè)之間的串行通訊(最大的波特率可達(dá)115200bps)。借助于IOB口的特殊功能和UART IRQ中斷，可以完成UART 接口的通訊功能。此外，SPCE061A還可以接收緩沖器內(nèi)容。 </p><p>　　4.13 音頻算法 </p

38、><p>　　在SPCE061A 中可使用以下幾種語(yǔ)音信號(hào)：SACM_S200, SACM_S480, SACM_S530, SACM_S720, SACM_A1600, SACM_A1601, SACM_A3600, SACM_DVR520, SACM_DVR1600, SACM_DVR3200, and SACM_DVR4800。至于音調(diào)合成，SPCE061A則提供了SACM_MS01 (FM synthesiz

39、er)和波表合成器。 </p><p>　　4.14 保密設(shè)定 </p><p>　　安全功能是為了保護(hù)代碼用來(lái)寫或者讀的.當(dāng)程序下載進(jìn)入到閃存內(nèi).程序可以用IDE工具來(lái)寫或者讀的.如果希望將內(nèi)部的閃存進(jìn)行保密設(shè)定，可將PFUSE 接5V, PVIN接GND并維持2s以上即可將內(nèi)部保險(xiǎn)絲熔化，此后就無(wú)法再完成下載, 調(diào)試等功能。 </p><p><b>

40、;　　5 結(jié)構(gòu)框圖</b></p><p><b>　　6 免責(zé)條款 </b></p><p>　　在這個(gè)版本出現(xiàn)的數(shù)據(jù)被相信是正確的.凌陽(yáng)科技所出售之集成電路僅受銷售條件中所規(guī)定擔(dān)保及專利賠償條款之規(guī)范。凌陽(yáng)科技對(duì)于本文件所載之信息或本文件所述芯片無(wú)侵害他人專利之情事，不負(fù)任何明示、法定默示或敘述性之擔(dān)保。另，不論為何目的使用，凌陽(yáng)科技不保證其市場(chǎng)性

41、及適合性。凌陽(yáng)科技保留隨時(shí)暫停生產(chǎn)或變更規(guī)格及價(jià)格之權(quán)利，而無(wú)須為任何通知。茲此敬告本文件閱讀者于發(fā)出訂單前應(yīng)確認(rèn)本文件所載資料表及其它信息系符合現(xiàn)況。本文件所述產(chǎn)品系擬為一般商業(yè)應(yīng)用之使用。涉及特殊環(huán)境或可靠性要求之應(yīng)用，例如軍事設(shè)備或醫(yī)療維生設(shè)備等，未經(jīng)凌陽(yáng)科技就此等應(yīng)用目的另行處理時(shí)，特別不建議之。敬請(qǐng)注意本文件所述應(yīng)用電路僅系供參考之用。 </p><p>　　16-BIT SOUND CONTROLLE

42、R</p><p>　　WITH 32K X 16 FLASH MEMORY</p><p>　　1 GENERAL DESCRIPTION </p><p>　　The SPCE061A, a 16-bit architecture product, carries the newest 16-bit microprocessor, μ’nSP?(pronoun

43、ced as micro-n-SP), developed by Sunplus Technology. This high processing speed assures the μ’nSP?is capable of handling complex digital signal processes easily and rapidly. Therefore, the SPCE061A is applicable to the a

44、reas of digital sound process and voice recognition. The operating voltage of 3.0V through 3.6V and speed of 0.32MHz through 49.152MHz yield the SPCE061A to be easily used in vari</p><p>　　2 FEATURES </p

45、><p>　　* 16-bit μ’nSP(TM) microprocessor </p><p>　　* CPU clock: 0.32MHz - 49.152MHz </p><p>　　* Operating voltage: 3.0V - 3.6V </p><p>　　* 2K-word working SRAM </p

46、><p>　　* 32K-word flash memory </p><p>　　* Software-based audio processing </p><p>　　* Crystal Resonator </p><p>　　* Standby mode (Clock Stop mode) for power savings,

47、Max.2.0μA @ VDD = 3.6V </p><p>　　* Two 16-bit timers/counters </p><p>　　* Two 10-bit DAC outputs </p><p>　　* 32 general I/Os (bit programmable) </p><p>　　* 14 INT s

48、ources with two priority levels </p><p>　　* Key wakeup function (IOA0 - 7) </p><p>　　* Approx. 190 sec speech @ 2.0Kbit/per sec with SACM_S200 </p><p>　　* PLL feature for system

49、clock </p><p>　　* 32768Hz Real Time Clock (RTC) </p><p>　　* Eight channels 10-bit AD converter ADC external top reference voltage </p><p>　　* Built-in microphone amplifier and AG

50、C function </p><p>　　* UART receiver and transmitter (full duplex) </p><p>　　* Low voltage reset and low voltage detection </p><p>　　* Security function to protect code to be rea

51、d and written. </p><p>　　3 APPLICATION FIELD </p><p>　　* Voice recognition products </p><p>　　* Intelligent interactive talking toys </p><p>　　* Advanced educationa

52、l toys </p><p>　　* Kids learning products </p><p>　　* Kids storybook </p><p>　　* General speech synthesizer </p><p>　　* Long duration audio products </p><

53、;p>　　* Recording / playback products </p><p>　　4 FUNCTIONAL DESCRIPTIONS </p><p><b>　　4.1 CPU </b></p><p>　　The SPCE061A is equipped with a 16-bit μ’nSP(TM), the new

54、est 16-bit microprocessor by Sunplus and pronounced as micro-n-SP. Eight registers are involved in μ’nSP(TM): R1 - R4 (General-purpose registers), PC (Program Counter), SP (Stack Pointer), Base Pointer (BP) and SR (Segme

55、nt Register). The interrupts include three FIQs (Fast Interrupt Request) and eight IRQs (Interrupt Request), plus one software-interrupt, BREAK. Moreover, a high performance hardware multiplier with the capability of FIR

56、 fi</p><p>　　4.2 Memory </p><p>　　4.2.1 SRAM </p><p>　　The amount of SRAM is 2K-word (including Stack), ranged from #0000 through #07FF with access speed of two CPU clock cycles.

57、 </p><p>　　4.2.2 Flash memory </p><p>　　Flash memory (#008000 - #00FFFF) is a high-speed memory with access speed of two CPU clock cycles. FLASH erase and program functions must be used in ID

58、E tools. </p><p>　　4.3 PLL, Clock, Power Mode </p><p>　　4.3.1 PLL (Phase Lock Loop) </p><p>　　The purpose of PLL is to provide a base frequency (32768Hz) and to pump the frequency

59、 from 20.48MHz to 49.152MHz for system clock (Fosc). The default PLL frequency is 24.576MHz. </p><p>　　(1)System clock Basically,the system clock is provided by PLL and programmed by the Port_SystemClock (W

60、) to determine the frequency of clock for system. The default system clock Fosc = 24.576MHz and CPU clock is Fosc/8 if not specified. The initial CPU clock is Fosc/8 after system wakes up and to be adjusted to desired

61、 CPU clock by programming the Port_SystemClock (W).This avoids Flash ROM reading failure when system wakes up. </p><p>　　(2)32768Hz RTC The Real Time Clock (RTC) is normally used in watch, clock or other t

62、ime related products. A 2Hz-RTC (1/2 second) function is loaded in SPCE061A. The RTC counts the timing as well as to wake CPU up whenever RTC occurs. Since the RTC is generated each 0.5 seconds, time can be traced by

63、 the numbers of RTC occurrence.In addition,SPCE061A supports 32768Hz oscillator in normal mode and auto-power-saving mode.In normal mode, 32768Hz OSC always runs at the highest power consumption</p><p>　　4.4

64、 Standby Mode </p><p>　　The SPCE061A also offers a standby mode for low power application needs. To enter standby mode, the desired key wakeup port (IOA [7:0]) must be configured to input first. And read

65、the Port_IOA_Latch(R) to latch the IOA state before entering the standby mode. Also remember to enable the corresponding interrupt source(s) for wakeup. After that, stop the CPU clock by writing the STOP CLOCK Register

66、 (b0-b2 of Port_SystemClock (W)) to enter standby mode. In such mode, SRAM and I/Os remain in the</p><p>　　4.5 Low Voltage Detection and Low Voltage Reset </p><p>　　4.5.1 Low voltage detectio

67、n (LVD) </p><p>　　There are two LVD levels to be selected: 2.9V, and 3.3V. These levels can be programmed via Port_LVD_Ctrl (W). As an example, suppose LVD is given to 2.9V. When the voltage drops below 2

68、.9V, the b15 of Port_LVD_Ctrl is read as HIGH. In such state, program can be designed to react to this condition. </p><p>　　4.5.2 Low voltage reset </p><p>　　In addition to the LVD, the SPCE

69、061A has another important function, Low Voltage Reset (LVR). With the LVR function, a reset signal is generated to reset system when the operating voltage drops below 2.3V for 10 consecutive CPU clock cycles.Without

70、LVR, the CPU becomes unstable and malfunctions when the operating voltage drops below 2.3V. The LVR will reset all functions to the initial operational (stable) states when the voltage drops below 2.3V. </p><

71、;p>　　4.6 Interrupt </p><p>　　The SPCE061A has 14 interrupt sources, grouped into two types, FIQ (Fast Interrupt Request) and IRQ (Interrupt request).The priority of FIQ is higher than IRQ. FIQ is the hi

72、gh-priority interrupt while IRQ is the low-priority one. An IRQ can be interrupted by a FIQ, but not by another IRQ.A FIQ cannot be interrupted by any other interrupt sources. </p><p><b>　　4.7 I/O &l

73、t;/b></p><p>　　Two I/O ports are built in SPCE061A, PortA and PortB.The PortA is an ordinary I/O with programmable wakeup capability. In addition to the regular IO function, the PortB can also perform som

74、e special functions in certain pins. Suppose operating voltage is running at 3.6V (VDD) and VDDIO (power for I/O) operates from 3.6V (VDD) to 5.5V. In such condition, the I/O pad is capable of operating from 0V throug

75、h VDDIO. However IOB13 and IOB14 are recommended to operate <=3.6V during standby mode, ot</p><p>　　Although data can be written into the same register through Port_Data and Port_Buffer, they can be read

76、 from different places, Buffer (R) and Data (R).The IOA [7:0] is the key wakeup port. To activate key wakeup function, latch data on PORT_IOA_Latch and enable the key wakeup function. Wakeup is triggered when the PortA

77、state is different from at the time latched. In addition to an ordinary I/O port, PortB carries some special functions. </p><p>　　4.8 Timer / Counter </p><p>　　The SPCE061A provides two 16-

78、bit timers/counters, TimerA and TimerB. The TimerA is called a universal counter.TimerB is ageneral-purpose counter.The clock source of TimerA comes from the combination of clock source A and clock source B.In TimerB, t

79、he clock source is given from source C.When timer overflows,an INT signal is sent to CPU to generate a time-out signal. Initially, write a value of N into a timer and select a desired clock source, timer will start coun

80、ting from N, N+1, N+2, ... th</p><p>　　The following example is a 3/16-duration cycle.The APWMO waveform is made by selecting a pulse width through Port_TimerA_Ctrl (W) [9:6].As a result,each 16 cycles wi

81、ll generate a pulse width defined in control port.These PWM signals can be applied for controlling the speed of motor or other devices. </p><p>　　Generally speaking,the clock source A and C are fast clock so

82、urces and source B comes from RTC system(32768Hz).Therefore,clock source B can be utilized as a precise counter for time counting,e.g.,the 2Hz clock can be used for real time counting. </p><p>　　4.8.1 Timeb

83、ase </p><p>　　Timebase, generated by 32768Hz,is a combination of frequency selections. The outputs of timebase block are named to TMB1 and TMB2.TMB1 is frequency for TimerA(Clock source B).The TMB1 and TMB2

84、 are the sources for Interrupt(IRQ6).Furthermore,</p><p>　　timebases generates additional 2Hz to 4096Hz interrupt sources (IRQ4 and IRQ5) for Real-Time-Clock (RTC).</p><p>　　4.9 Sleep, Wakeup

85、 and Watchdog </p><p>　　4.9.1 Wakeup and sleep </p><p>　　1) Sleep: After power-on reset,IC starts running until a sleep command occurs.When a sleep command is accepted, IC will turn the system

86、clock (PLL) off. After all, it enters sleep mode. </p><p>　　2) Wakeup: CPU waking up from sleep mode requires a wakeup signal to turn the system clock (PLL) on.The IRQ signal makes CPU to complete the wakeu

87、p process and initialization.The key wakeup and interrupt sources (IRQ1 - IRQ6) can be used for wakeup sources. </p><p>　　4.9.1 Watchdog </p><p>　　The purpose of watchdog is to monitor if th

88、e system operates normally. Within a certain period, watchdog must be cleared. If watchdog is not cleared, CPU assumes the program has been running in an abnormal condition. As a result, the CPU will reset the system

89、to the initial state and start running the program all over again. The watchdog function can be removed by bonding option. In SPCE061A, the clear period is 0.75 seconds.If watchdog is cleared within each 0.75 seconds,

90、the system will n</p><p>　　4.10 ADC(Analog to Digital Converter)/DAC </p><p>　　The SPCE061A has eight channels 10-bit ADC (Analog to Digital Converter).The function of an ADC is to convert anal

91、og signal to digital signal, e.g. a voltage level into a digital word.The eight channels of ADC can be seven channels of line-in from IOA[6:0] or one channel microphone (MIC) input through amplifier and AGC controller.Th

92、e MIC amplifier circuit is capable of reducing common mode noise by transmitting signals through differential MIC Inputs(MICN, MICP). Moreover, an external resistor </p><p>　　4.11 Serial Interface I/O (SIO

93、) </p><p>　　Serial interface I/O offers a one-bit serial interface for communication.This serial interface is capable of transmitting or receiving data via two I/O pins, IOB0 (SCK) and IOB1 (SDA).</p>

94、<p>　　4.12 UART </p><p>　　UART block provides a full-duplex standard interface that facilitates the communication with other devices.With this interface, SPCE can transmit and receive simultaneously.T

95、he maximum baud-rate can be up to 115200bps. </p><p>　　4.13 Audio Algorithm </p><p>　　The following speech types can be used in SPCE061A: PCM,The functions of IDE include the follows:SACM_S2

96、00,SACM_S480,SACM_S530,SACM_S720, SACM_A1600,SACM_A1601,SACM_A3600,SACM_DVR520,SACM_DVR1600,SACM_DVR3200,and SACM_DVR4800.For circuit-(7).melody synthesis,the SPCE061A supports SACM_MS01(FM) . </p><p>　　4.14

97、 Security Function </p><p>　　Security function is able to protect code to be read or written. When program is downloaded into flash memory, program can be read/written from IDE tools. For security purpose,

98、 burn fuse to disable IDE function, where PFUSE supplies 7.0V and PVIN connects to ground (0V) about one second (Please refer to the following circuit diagram).After all, the flash memory can no longer be read or writte

99、n. </p><p>　　5 BLOCK DIAGRAM </p><p>　　6 DISCLAIMER </p><p>　　The information appearing in this publication is believed to be accurate. </p><p>　　Integrated circuits

100、sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the in

101、formation in this publication or regarding the freedom of the described chip(s) from patent infringement. Further, sunplus makes no warranty of merchantability or fitness for any purpose. SUNPLUS reserves the right t

102、o halt production or alter the specifica</p><p>　　Applications involving unusual environmental or reliability requirements,e.g. military equipment or medical life support equipment, are specifically not reco