外文翻譯--基于dds參數(shù)可調(diào)諧波信號發(fā)生器的研究

1、1中文 中文 2330 2330 字畢 業(yè) 設(shè) 計（論 計（論 文）附 文）附 件外 文 文 獻 翻 譯學(xué) 號： 號： 姓 名： 名： 所在院系： 所在院系： 數(shù)理系 專業(yè)班級： 專業(yè)班級： 指導(dǎo)教師： 指導(dǎo)教師： 原文標(biāo)題： 原文標(biāo)題： Research of Paramet

2、er Adjustable Harmonic Signal Generator Based on DDS 2014 2014 年 6 月 10 10 日898889978-0-7695-3290-5/08 $25.00 © 2008 IEEE 88DOI 10.1109/CCCM.2008.11The goal of the system is to design a

3、 harmonic signal generator, whose frequency, phase and harmonic proportion are adjustable. The output waveform is composed of fundamental wave, 3th harmonic, 5th harmonic and 7th harmonic. Frequency resolution is

4、1Hz. The adjustable range of initial phase is 0~2π and its resolution is 1o. The adjustable range of harmonic proportion is 0~50% and its resolution is 1%.According to the design requirements, system clock frequency i

5、s 15MHz and phase accumulator is 24-bit. In order to make the most of EAB, 211×8 bits ROM table is adopted. 11-bit phase control word is used to meet the requirement of initial phase resolution. 7-bit proportion

6、 control word is adopted to realize the setting of harmonic proportion.3.2. Algorithm of ROM compressionAs is known, phase truncation error is the main factor of output waveform distortion. To avoid this, the ROM size

7、must be exponentially increased, however the EAB of FPGA is limited. So the algorithm of ROM compression based on the symmetry of sine wave is adopted in the system.Sine wave of one period is divided into 4 sections:

8、[0~π/2] 、 [π/2~π] 、 [π~3π/2] 、 [3π/2~2π]. Using thesymmetry of sine wave, sampled amplitudes of the first section are stored in the ROM table. By address conversion and amplitude conversion, sampled amplitudes

9、 of one period sine wave can be generated. By this means, the ROM size is a quarter of the previous size. In the same ROM, sampling points can be increased by 4 times with this method [3]. The structure diagram of the

10、 algorithm is shown in Fig.2.Figure 2. Structure diagram of ROM compression AlgorithmIn the above structure diagram, the address of ROMtable is L-bit. Sampled amplitudes of quarter wave are stored in the ROM table. The

11、 output address of phase accumulator is (L+2)-bit. The low L-bit are used to query the ROM table while the high 2-bit are used to identify phase sections. When the highest bit is 1, the output of ROM table should be

12、symmetrically converted by the amplitude convertor. When the second highest bit is 1, the L-bit address should be symmetrically converted by the address convertor.4. System design based on FPGAThe system can be divided

13、 into two function modules: sine wave generation module and harmonic synthesis module. Sine wave generation module is the key part of the system. It can be divided into phase accumulator module and ROM compression mod

14、ule [4]. Altera FPGA EP2C5Q208C8 is adopted as the core component of the system. VHDL is used to program the whole system. Compilation and simulation are implemented in Quartus Ⅱ.4.1. Sine wave generation moduleBlock

15、 diagram of sine wave generation module is shown in Fig.3.Figure 3. Block diagram of sine wave generation moduleIn the above block diagram, phase accumulator moduleis composed of 24-bit accumulator and 11-bit adder. Und

16、er the control of system clock, the output of 24-bit accumulator is accumulated with 9-bit frequency control word. Then 11-bit adder adds 11-bit phase control word to the output of accumulator. High 13-bit of the fina

17、l result are used as address to query the ROM compression module [5].ROM compression module is composed of address convertor, amplitude convertor and ROM table. 13-bit address of phase accumulator module is divided in

18、to three parts [6]. The highest bit is used as trigger signal of the amplitude convertor. The second highest bit is used as trigger signal of the address convertor. The low 11-bit are used to query the ROM table. The