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1、華中科技大學(xué)碩士學(xué)位論文基于H.264標(biāo)準(zhǔn)的插值技術(shù)研究姓名:楊先勇申請(qǐng)學(xué)位級(jí)別:碩士專業(yè):計(jì)算機(jī)系統(tǒng)結(jié)構(gòu)指導(dǎo)教師:周敬利20070129II Abstract With the development of the techniques in storage, communication, processor and the increase of high quality video service requirement, a l
2、ot of new techniques are proposed in video coding field, such as intra prediction, variable block size motion compensation, quarter sample accurate motion estimation, 4×4 block size transform and so on. H.264 which
3、adopts these techniques is the newest international video coding standard. Extrapolation technique of intra prediction in H.264 is used to generate the prediction block from previously encoded and reconstructed blocks of
4、 current frame. This technique is based on directional spatial texture concept. Analysis of this technique revealed two problems: First, known information has not been fully utilized, when all the reference pixels are av
5、ailable, only 30%~60% can be used; Second, gradational property of spatial texture hasn't been taken into account, simply replicate operation is premised on that all the pixels don't change in the same directiona
6、l spatial texture. A new extrapolation technique of intra prediction is proposed to predict the gradational trend in the same directional spatial texture by utilizing the rest available information. Experiment results sh
7、ow that proposed extrapolation technique of intra prediction has better rate distortion performance with slightly computation complexity increasing. Interpolation technique of inter prediction in H.264 is used in quarte
8、r sample accurate motion estimation to generate the fractional pixels by applying FIR filter horizontal and vertical. Analysis revealed that this technique lead to the computation and memory access bottleneck. A new 4 ta
9、p FIR filter [-3, 19, 19, -3]/32 is designed and a new interpolation technique is accordingly proposed. Complexity analysis and experiment results show that compared with interpolation technique in H.264, 10% memory acce
10、ss and 18.2% computation complexity are reduced by the proposed technique with slightly rate distortion performance degrading. Proposed technique is more suitable for implementing real time video codec on VLSI, DSP chips
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