畢業(yè)論文外文翻譯(無線局域網(wǎng)接收器的高效自動增益控制算法和結(jié)構(gòu))

1、<p>　　無線局域網(wǎng)接收器的高效自動增益控制算法和結(jié)構(gòu)</p><p>　　Il-Gu Lee *, Sok-Kyu Lee</p><p>　　下一代無線局域網(wǎng)研究團隊，電子和電信研究院，柯亭161棟，顧儒城區(qū)，大田305700，大韓民國</p><p>　　2006年2月23日收稿；2006年10月31日收到修訂的稿件；2006年11月1日收錄<

2、;/p><p>　　2007年1月11日可在線使用</p><p><b>　　摘要</b></p><p>　　接收機的性能前端限制了所給定的通信鏈路的質(zhì)量和范圍?；诿鞔_定義的系統(tǒng)參數(shù)和結(jié)構(gòu)的設(shè)計可以使整個系統(tǒng)在性能、成本和市場化方面有巨大的差異。值得強調(diào)的是，我們需要一種改進的數(shù)字自動增益控制(AGC)，應(yīng)用于多輸入多輸出、正交頻分復(fù)用(mi

3、mo - ofdm)的無線局域網(wǎng)(WLANs),爭取成為即將到來的802.11n標準（在2004年8月，Heejung Yu et al.建議采用無線ETRI局域網(wǎng)作為泰科全球網(wǎng)絡(luò)、IEEE 802.11文件（文件號11-04-0923-00-000n）的說明; H.Yu,T.Jeon,S.Lee,為下一代無線局域網(wǎng)設(shè)計的雙頻MIMO-OFDM系統(tǒng)在2005年5月電機及電子學(xué)工程師聯(lián)合會通信國際會議（ICC）上獲得通過）。在本文中，我們

4、提出一種有效的算法和實施面向下一代無線局域網(wǎng)的數(shù)字自動增益控制系統(tǒng)。該自動增益控制算法有兩個反饋增益控制以提高收斂速度,且同時保持AGC電路的穩(wěn)定性。另外，在各種滿足不動點約束和精度要求的實驗中獲得了實際應(yīng)用中需要的一套完整參數(shù)。</p><p>　　關(guān)鍵詞：自動增益控制，無線局域網(wǎng); MIMO-OFDM技術(shù)，接收器結(jié)構(gòu)</p><p><b>　　1、簡介</b>&

5、lt;/p><p>　　AGC電路應(yīng)用于許多系統(tǒng)，這些系統(tǒng)的輸入信號電平在非常大的動態(tài)范圍內(nèi)變化。在高數(shù)據(jù)傳輸速率的數(shù)字通信系統(tǒng)中，尤其是在突發(fā)包分組交換系統(tǒng)中，如無線局域網(wǎng)，每個數(shù)據(jù)包開始會引入了一個大信號變化。來解調(diào)一個改善信噪比的接收信號，自動增益控制可用于維持基帶信號的平均功率在我們期望值的附近。 AGC對于應(yīng)用于下一代無線局域網(wǎng)技術(shù)的MIMO-OFDM具有重要意義，它確保實現(xiàn)接收端的性噪比滿足實際要求，從而

6、確保實數(shù)據(jù)傳輸速率。</p><p>　　過去已經(jīng)有一些關(guān)于自動增益控制的研究，這些研究提出自動增益控制算法和目前實施所遇到的問題。在文獻[3,4]中，作者提出了一種實現(xiàn)簡單的數(shù)字自動增益控制結(jié)構(gòu)，其定位于IEEE802.11a標準。文獻[3]的作者提出一種簡單的多站式自動增益控制方案。在文獻[4]中，作者提出了一種基于雙自相關(guān)的同步自動增益控制接口的方案。在這些論文中，對理論問題進行了分析，并且提供了沒有詳細考

7、慮實施過程中的限制條件而得到的仿真結(jié)果。</p><p>　　在本文中，提出了新的AGC結(jié)構(gòu)，它包括一個大增益更新循環(huán)和一個小增益更新循環(huán)，用來提高收斂速度，并同時保持AGC電路的穩(wěn)定。此外，它還可以動態(tài)控制MIMO- OFDM系統(tǒng)接收到大變化能量信號的增益，該信號能量變化由隨時間頻率偏移的多徑衰落引起的。</p><p>　　本文的其余部分安排如下：在第二節(jié)中，給出下一代無線局域網(wǎng)的框架

8、模型；在第三節(jié)中，描述了接收器的整體結(jié)構(gòu)。后面詳細地描述每個子塊，并給出各自部分結(jié)構(gòu)：自動增益控制在第4節(jié)；數(shù)字放大器在第5節(jié)載以及波監(jiān)聽在第6節(jié)；在第7節(jié)中，展現(xiàn)該設(shè)計的性能；最后，在第8節(jié)我們得出結(jié)論。</p><p><b>　　2、框架模型</b></p><p>　　下一代WLAN是一種基于分組的高通量MIMO - OFDM系統(tǒng)，該系統(tǒng)工作在 5 GHz頻帶

9、。圖1和2顯示了下一代無線局域網(wǎng)的數(shù)據(jù)包結(jié)構(gòu) ，該結(jié)構(gòu)在文獻[1,2]中有詳細描述。每個數(shù)據(jù)包包含一個檢測頭， 預(yù)測信道和同步信道。報頭可以被雙方識別以用來通信鏈接。傳統(tǒng)的OFDM報頭由10個相同的短正交頻分復(fù)用(OFDM)輔助符號（ti，i = 1，2……10；每個符號包含16個樣品）和2個相同的長正交頻分復(fù)用(OFDM) 輔助符號（Ti，i = 1，2；每個符號包含64個像IEEE802.11a的樣品）。在MIMO- OFDM模式，

10、長正交頻分復(fù)用(OFDM)符號，（Ti，i = 1，2），該符號在信號之后傳輸，提供信道測量能力。短的輔助符號是用于信號檢測，自動增益控制，多樣性，粗采樣和頻率同步。為了確保接收到的信號增益控制及時和提供穩(wěn)定增益的可靠傳輸，接收器設(shè)計人員可以使用短報頭來調(diào)整接收到的信號強度達到到最佳水平，該調(diào)整通過在接收信號路徑上可動態(tài)調(diào)節(jié)的各種信號處理元件來實現(xiàn)。</p><p>　　圖1 傳統(tǒng)的OFDM數(shù)據(jù)包結(jié)構(gòu)模型<

11、;/p><p>　　圖2 MIMO-OFDM數(shù)據(jù)包結(jié)構(gòu)模型</p><p>　　長輔助符號被設(shè)計用來信道預(yù)測和精細頻移校正。該信號包括奇偶校驗，長度和速率等。有一個短的保護區(qū)間（GI）和一個長的保護區(qū)間（GI2）組成32或64個數(shù)據(jù)樣本，分別用來作為傳統(tǒng)OFDM的長輔助符號和長MIMO - OFDM的輔助符號。在OFDM數(shù)據(jù)域中，每個波段有四個子載波作為試點被插入到的位置-21，-7，7，和

12、21。，子載波總數(shù)分別為52和104。</p><p><b>　　3、接收器結(jié)構(gòu)</b></p><p>　　接收器的整體框圖如圖3所示。從三個天線接收到的3個信號 輸入數(shù)字放大器用來調(diào)整即將到來信號的能力達到目標值。數(shù)字前端操作只適用于來自3個可用路徑出來的兩個接收信號，達到降低實施復(fù)雜度的目的。輸入信號能量測量和增益更新是在AGC模塊中計算的。數(shù)字放大器的輸出被

13、監(jiān)測用來檢測信號是否太大或者太小大而超出載波的敏感范圍。接收到的信號被引向到一個+10和-10M赫茲頻率變化的頻道混合器。OFDM輸入符號緩沖到FFT輸入緩沖區(qū)，并且在輸入FFT前對載波頻率偏移（CFO）進行糾正。利用相導(dǎo)頻跟蹤塊對頻率和相位的誤差進行估計和糾正。通過短報頭和長報頭的自相關(guān)的結(jié)果來實現(xiàn)CFO估計，幀同步和帶檢測。同步程序完成后，CFO補償數(shù)據(jù)包由128點、基-23 DIF FFT塊轉(zhuǎn)化為頻域。該FFT輸出是位反轉(zhuǎn)順序，該

14、序列通過使用迫零（ZF）方法輸入到MIMO檢測中[2]。ListenJiēshōu dào de xìnhào bèi dìngxiàng dào yīgè tōngdào hùnhé qì wèi 10 hé 10 zhào hè de pínlǜ fāshēng b

15、iànhuà. OFDM fúh</p><p>　　圖3 帶3天線的雙頻段MIMO-OFDM接收機前端結(jié)構(gòu)</p><p><b>　　4、自動增益控制</b></p><p>　　接收信號幅度的自動調(diào)整使得ADC的動態(tài)范圍得以充分利用。AGC實際工作的狀態(tài)轉(zhuǎn)移圖如圖4所示。當AGC自動增益控制塊的啟動信號（a

16、gc_en）為低電平時，該自動增益控制塊的狀態(tài)從任意狀態(tài)變成空閑狀態(tài)。第一個狀態(tài)是功率測量狀態(tài)（MSR），它判定在放大器增益調(diào)整之前信號峰值是否在ADC的動態(tài)范圍之內(nèi)。如圖5所示，信號功率的衡量是根據(jù)每個天線積累的實部絕對值（同相分量）和虛部（正交分量）的能量來測量信號的信號功率。用0.8最小二乘方法（32個在40 MHz采樣的樣本）來測量輸入信號的功率。所選擇的轉(zhuǎn)換為，通過采用信號能量的對數(shù)值可以減少信號能量值的范圍。如果在信號功率測

17、量期間，測量得到的信號能力不在ADC（ADC飽和度）的動態(tài)范圍內(nèi)，能量測量將停止，同時AGC啟用大的增益更新狀態(tài)（Update_L），用大的增益控制值來粗調(diào)增益以加快增益調(diào)整。通過寄存器的設(shè)定值（agc_gainl）來迅速降低放大器的增益，以達到加速收斂的目的。增益調(diào)整的尺度固定為3分貝。在信號功率測量期間，增益更新是由于在ADC飽和度觀察時候ADC已經(jīng)飽和如果在信號功率測量期間，ADC沒有飽和度，則測量的能量和參考能量進行比</

18、p><p>　　圖4 AGC狀態(tài)轉(zhuǎn)移圖</p><p>　　圖5 AGC方框圖</p><p><b>　　5、數(shù)字放大器</b></p><p>　　數(shù)字放大器是通過放大或衰減來調(diào)整信號能量的大小，它根據(jù)現(xiàn)有的增益狀態(tài)調(diào)整可編程寄存器使得信號能量達到目標能量。數(shù)字放大器包括一個增益狀態(tài)單元，它可以存儲對接收的數(shù)據(jù)包處理

19、所選定的增益狀態(tài)該增益狀態(tài)單元從最高增益狀態(tài)開始，以確保最低的功率信號可以被檢測和處理。兩個??接收信號的路徑上都應(yīng)用到了相同的增益調(diào)整量。利用像圖6所示的粗增益步驟，簡化了數(shù)字放大器的實施。更新的增益量劃分為6分貝和3分貝兩個步驟， 6分貝增益更新步驟首先應(yīng)用到輸入信號，然后再用3分貝步驟進行增益調(diào)整。當增益控制值和AGC參考值相同時，將不存在增益調(diào)整。</p><p>　　圖6 數(shù)字放大器的方框圖</

20、p><p>　　6、監(jiān)控ADC飽和的載波監(jiān)聽</p><p>　　不管ADC是否飽和，輸入信號的存在都可以通過監(jiān)測被檢測到。為了提高ADC飽和度檢測的可靠性，使用16個在40 MHz采樣的連續(xù)樣品?？紤]一個從天線0接收到的信號的實部部分。如果ADC輸出樣本的數(shù)值絕對值大于某個閾值（cs_th_sat，500），且大于或等于一個可編程的寄存器數(shù)值（cs_th_cnt_sat，4），我們就標記AD

21、C已經(jīng)達到飽和。 4個信號的組成部分（兩個天線接收到信號的實部和虛部）中任意一個都可以標記ADC已經(jīng)達到飽和。載波監(jiān)聽的框圖如圖7所示。</p><p>　　圖7 載波監(jiān)聽的方框圖</p><p><b>　　7、性能評估</b></p><p>　　我們運用了50 ns的均方根時延擴展信道模型。同時，該模型包括射頻損傷和一個具有10 dB補

22、償?shù)睦展β史糯笃骱鸵粋€具有零極點相位噪聲的模型。發(fā)射機和接收機振蕩器的頻率不穩(wěn)定會引起殘留頻率誤差的存在。由于模數(shù)轉(zhuǎn)換器（ADC）的使用，使得所有仿真事件都有時間/頻率偏移。數(shù)據(jù)包大小固定為1 K字節(jié)。仿真模型的傳輸速率固定為36 Mbps（兆比特每秒）和54 Mbps（兆比特每秒），使用QPSK，16 -QAM和64- QAM的調(diào)制方案，這些方案都采用MIMO雙波段技術(shù)。因此，實際的數(shù)據(jù)傳輸速率分別為72 Mbps（兆比特每秒）的，

23、144 Mbps（兆比特每秒）和216 Mbps（兆比特每秒）。</p><p>　　使用不同的調(diào)制方案仿真得到的包差錯率繪制在圖8上。FL和FX分別指仿真結(jié)果中的浮點類型和定點類型。雖然大多數(shù)調(diào)制方案的定點與浮點有相似的性能，然而在使用16 -QAM和64- QAM的調(diào)制方案時，由量化誤差引起的性能上的差距很明顯，在10％的包差錯率時，兩種方案損失的信噪比分別為0.3和0.7分貝。我們在圖8表明：推薦的算法及其

24、實施在多徑衰落的50ns均方根時延擴展和40 ppm的時間/頻率偏移中具有很好的效果。就已知的約束而言，該算法在28分貝信噪比大約有10％包差錯率?？紤]到實施的復(fù)雜性和性能之間的折中，我們提出的算法和它的實施對于MIMO- OFDM系統(tǒng)接收器而言，是一個很好的折中解決方案。</p><p>　　圖8 調(diào)制方案在包差錯率之間的比較</p><p>　　在圖9中，在16-QAM和R= 3/

25、4條件下，目標信號在仿真過程中的幅度調(diào)整變化。agc_vref是在3分貝條件下，在AGC完成之后的目標信號幅度。例如，agc_vref= 13對應(yīng)著目標信號的幅度為2 ^ （13/2）。我們發(fā)現(xiàn)，通過對信號頻帶的使用和雙頻段的使用進行不同的設(shè)置，接收機的性能可以得到提高，如表1所示。如表2所示，agc_gainl和agc_gains寄存器值的設(shè)置需要考慮包差錯率的結(jié)果，和輸入信號的能量范圍和更新的次數(shù)，因為AGC需要在短報頭結(jié)束之前很好

26、的完成。agc_init是初始增益設(shè)置。如果信號需要被放大，初始增益將增加到最大值。如果信號很大，需要加以抑制，初始增益將減少到0。當agc_ginit是20，增益控制為3分貝時，最大的信號抑制可達到20*3 = 60分貝，最大的信號放大可以達到（32-20）*3 = 36分貝。初始增益應(yīng)該設(shè)置得足夠大以達到具有抑制信號的能力。在agc_ginit= 20這個例子中，有60分貝的空間去抑制信號。自動增益控制寄存器仿真參數(shù)的設(shè)置如表1所示

27、。</p><p>　　圖9 AGC參考值 (agc_vref)的調(diào)整</p><p>　　表1 可編程寄存器的設(shè)置</p><p>　　表2 AGC循環(huán)次數(shù)</p><p>　　接收器中AGC的快速收斂電路減少了將接收信號調(diào)整到ADC工作范圍內(nèi)的時間。本文提出的的數(shù)字AGC電路包括一個大增益更新循環(huán)和一個小增益更新循環(huán)，用來加快收斂速

28、度，并且同時維持控制輸入信號電平穩(wěn)定。圖10為1000包，在27分貝、64 - QAM和R= 3 /4 條件下的仿真結(jié)果。大增益更新循環(huán)可以很快的將接收信號調(diào)整到期望的范圍。小增益更新循環(huán)慢慢撫平接收信號，以避免AD轉(zhuǎn)換器達到飽和并且加輸入信號電平的收斂快速度。</p><p>　　數(shù)字放大器輸入信號電平與時間關(guān)系</p><p>　　數(shù)字放大器輸出信號電平與時間關(guān)系</p>

29、<p>　　圖10 數(shù)字放大器輸入/輸出信號電平</p><p><b>　　8、結(jié)論</b></p><p>　　在本論文中，設(shè)計的自動增益控制電路用來調(diào)整接收信號的強度，通過接收路徑上可以處理各種信號的大動態(tài)范圍元件來使接收信號達到一個恒定的最佳能量水平附近。該自動增益控制電路包括一個大增益更新循環(huán)和一個小增益更新循環(huán)，用來加快收斂速度，并且同時保持自

30、動增益控制電路的穩(wěn)定。此外，它可以用來動態(tài)控制由多徑衰落、時間和頻率偏移引起大變化范圍接收信號的增益， 以確保及時地對接收信號進行增益控制，提供穩(wěn)定增益進而得到可靠的傳輸。</p><p><b>　　參考文獻</b></p><p>　　[1] Heejung Yu et al., IEEE 802.11 wireless LANs ETRI proposal s

31、peci?cation for IEEE 802.11 TGn, IEEE 802.11 document, doc. No. 1104092300000n, August, 2004.</p><p>　　[2] H. Yu, T. Jeon, S. Lee, Design of dualband MIMO-OFDM system for next generation wireless LAN, in: IE

32、EE International Conference on Communications (ICC), May, 2005.</p><p>　　[3] V.P.G. Jimenez, M.J.F.G. Garcia, F.J.G. Serrano, A.G. Armada, Design and implementation of synchronization and AGC for OFDMbased W

33、LAN receivers, IEEE Trans. Consum. Electron. 50 (4) (2004) 1016–1025.</p><p>　　[4] A. Fort, W. Eberle, Synchronization and AGC proposal forIEEE 802.11a burst OFDM systems, GLOBECOM 3 (12) (2003) 1335–1338.&l

34、t;/p><p>　　E?cient automatic gain control algorithm and architecture for wireless LAN receivers</p><p>　　IlGu Lee *, SokKyu Lee</p><p>　　Next Generation Wireless LAN Research Team, ETR

35、I, 161 Gajeongdong, Yuseonggu, Daejeon 305700, Republic of Korea</p><p>　　Received 23 February 2006; received in revised form 31 October 2006; accepted 1 November 2006</p><p>　　Available online

36、11 January 2007</p><p><b>　　Abstract</b></p><p>　　The performance of a receiver frontend limits the quality and range of the given communication link. An appropriate design based on

37、wellde?ned system parameters and architecture can make a huge di?erence in the performance, cost and marketability of the entire system. In particular, there is a need for improved digital automatic gain control (AGC) fo

38、r use in multiinput multioutput orthogonal frequency division multiplexing (MIMOOFDM) systems with application to wireless local area networks (WLAN</p><p>　　Keywords: AGC; WLAN; MIMOOFDM; Receiver architect

39、ure</p><p>　　1. Introduction</p><p>　　AGC circuits are employed in many systems where the level of an incoming signal can vary over a wide dynamic range. In high data rate digital communication

40、systems, and especially in burst packet switched systems such as WLANs, the start of each packet introduces a large signal variation. To demodulate a received signal with an improved signaltonoise ratio, AGC can be used

41、to hold the average power of the baseband signal close to a desired level. AGC implementation of highthroughput MIMOOFDM app</p><p>　　There have been several research contributions that provide automatic gai

42、n control algorithms and present implementation issues. In [3,4], the authors present the implementation of a simple digital automatic gain control architecture targeting the IEEE 802.11a standard. The authors of [3] pro

43、pose a simple multistop AGC scheme. In [4],an AGC interface with a synchronization scheme based on double autocorrelation is proposed. In those papers, the theoretical problem is analyzed and simulation resu</p>&

44、lt;p>　　In this paper, the proposed architecture includes a large gain update loop and a small gain update loop to improve convergence speed and at the same time maintain the stability of the AGC circuit. Moreover, it

45、can be used to dynamically control the gain of the received signal for MIMOOFDM systems with large variations in received signal power caused by multipath fading with time and frequency o?set.</p><p>　　The r

46、emainder of this paper is organized as follows. In Section 2, the frame model is given for next generation wireless LANs, and the overall receiver architecture is presented in Section 3. A detailed description for each s

47、ubblock is then provided in their respective sections: automatic gain control in Section 4; carrier sensing block in Section 5; and digital ampli?er in Section 6. In Section 7, the performance of the proposed design is s

48、hown. Finally, we conclude in Section 8.</p><p>　　2. Frame model</p><p>　　The next generation WLAN is a packetbased highthroughput MIMOOFDM system in the 5 GHz band. Figs. 1 and 2 show the packe

49、t structure of next generation WLAN as speci?ed by [1,2]. Each packet contains a header for detection, channel estimation and synchronization. This preamble is known at both sides of the communication link. The legacy OF

50、DM packet preamble consists of 10 identical short OFDM training symbols ti, i =1,2, ...,10, each of which contains 16 samples; and two identical long OFDM symbo</p><p>　　Fig. 1. The packet structure of the L

51、egacy OFDM mode.</p><p>　　Fig. 2. The packet structure of the MIMO-OFDM mode.</p><p>　　The long training symbols are designed to be used for channel estimation and ?ne frequency o?set correction

52、. The signal ?eld includes information for parity, length and rate, etc. There is a short guard interval (GI) and a long guard interval (GI2) that consist of 32 or 64 data samples for the long legacyOFDM training symbol

53、and the long MIMOOFDM training symbol, respectively. In the OFDM data ?eld, four subcarriers are inserted as pilots into positions 21, 7, 7, and 21 for each band. The total </p><p>　　3. Receiver architecture

54、</p><p>　　The overall receiver block diagram is shown in Fig. 3. The three received signals from 3 antennas are fed into digital ampli?ers to adjust the power of the incoming signals to the target value. The

55、 digital front end operations are applied to only the two received signals out of the 3 available paths to reduce implementation complexity. The power of the input signal is measured and gain update is calculated in the

56、AGC block. The digital ampli?er output is monitored to detect if the signal is larg</p><p>　　I/Q imbalance that come from RF components and ADC are compensated in each signal path. The received signals are d

57、irected to a channel mixer for +10 and 10 MHz frequency shifting. The input OFDM symbol is bu?ered into the FFT input buffer, and the carrier frequency o?set (CFO) is corrected at the input of the FFT. The frequency and

58、phase errors are estimated and corrected by using the pilot tones in the phase tracking block. The CFO estimation, frame synchronization and band detection are perfor</p><p>　　Fig. 3. The front-end architect

59、ure of dual-band MIMO-OFDM receiver with 3 antennas.</p><p>　　4. Automatic gain control</p><p>　　The amplitude of the received signal is adjusted so that the dynamic range of the ADC can be full

60、y utilized. The state transition diagram implemented physically for the AGC is shown in Fig. 4. The AGC block state is changed to the idle state from whatever state the AGC is in when the AGC block enable (agc_en) is dea

61、ctivated. The ?rst state is a power measurement state (MSR), which determines whether the peak signal is within the dynamic range of ADC before adjusting the ampli?er gain. As shown i</p><p>　　maximize the s

62、ignal to noise ratio and minimize saturation e?ects. If the measured power (agc_pwr_log)is smaller than the target power (agc_vref), which is a programmable register, then the gain is adjusted so that the signal power is

63、 equal to the target power given by the register value after the signal is settled down for the gain change. If the measured signal power is larger than the target power, then the gain is reduced even more given the agc_

64、gains, which is register programmable. This ad</p><p>　　Fig. 4. State digram of AGC block.</p><p>　　Fig. 5. Block diagram of AGC.</p><p>　　5. Digital ampli?er</p><p>　　

65、The digital ampli?er is used to scale the incoming signal power either by amplifying or attenuating and adjusts it to the target power speci?ed in a programmable register according to the current gain state. The digital

66、ampli?er includes a gain state unit that stores the selected gain state for processing of a received packet. The gain state unit begins with the highest gain state to ensure the lowest power signals can be detected and p

67、rocessed. The same amount of gain adjustment is applied to t</p><p>　　Fig. 6. Block diagram of digital ampli?er.</p><p>　　6. Carrier sense by monitoring ADC saturation</p><p>　　The

68、existence of the incoming signal is detectedby monitoring whether the ADC is saturated or</p><p>　　not. To improve the reliability of detecting the ADC saturation, 16 consecutive samples at 40 MHz sampling a

69、re used. Consider one signal component that is a real component from antenna 0. If the number of ADC output sample whose absolute value is larger than a certain threshold (cs_th_sat, 500) is larger than or equal to a reg

70、ister programmable value (cs_th_cnt_sat, 4), then we ?ag that the ADC is saturated. Any one of the 4 signalcomponents (real and imaginary components from the two antennas) </p><p>　　Fig. 7. Block diagram of

71、carrier sensing.</p><p>　　7. Performance evaluation</p><p>　　We apply a 50 ns RMS delay spread channel model. As well, RF impairments, a RAPP power ampli?er with 10 dB backo? and phase noise wit

72、h a polezero model, are included. There can be a residual frequency error caused by frequency instabilities in the oscillators at the transmitter andreceiver. All simulation cases have time/frequency o?set, introduced by

73、 an analogtodigital converter (ADC). Packet size is ?xed to 1 K bytes. Simulation modes are ?xed to 36 Mbps and 54 Mbps, employing the QPSK, 16QAM </p><p>　　The simulated PER using di?erent modulation scheme

74、s is plotted in Fig. 8. FL and FX refer to the simulated result of ?oating point version and ?xed point version, respectively. Although most modulation schemes of ?xed point have similar per formance with ?oating point,

75、a performance gap due to quantization error is apparent when a 16QAM and 64QAM modulation scheme is utilized, resulting in 0.3 and 0.7 dB SNR loss at PER 10%,respectively. We show that the proposed algorithms and their i

76、mplementat</p><p>　　implementation complexity and the performance, our proposed algorithms and their implementation stand as a good compromised solution for MIMOOFDM receivers.</p><p>　　Fig. 8.

77、Modulation schemes vs. PER.</p><p>　　In Fig. 9, the target signal amplitude is adjusted through simulation under 16QAM and R = 3/4.</p><p>　　The agc_vref is the target signal amplitude afterAGC

78、is done in terms of the 3 dB step. For example, agc_vref = 13 corresponds to the target signal amplitude of 2^(13/2). We found that the receiver performance is improved by using di?erent settings for signal band use and

79、dual band use, as shown in Table 1. As shown in Table 2, the agc_gainl and agc_gains register values are set considering the PER result, and the range of the input signal power and the number of updates since the AGC sho

80、uld be </p><p>　　Fig. 9. AGC reference value (agc_vref) adjustment.</p><p>　　Table 1 Programmable register setting</p><p>　　Table 2 AGC loop counts</p><p>　　Faster co

81、nvergence of a receiver’s AGC circuit reduces the time required to bring a received signal within the operating range of ADC. The proposed digital AGC circuit includes a large gain update loop and a small gain update loo

82、p to improve con vergence speed and maintain stability of the controlled input signal level at the same time, as shown in Fig. 10 and simulated at 27 dB with</p><p>　　1000 packets, 64QAM and R = 3/4. The lar

83、ge gain update loop quickly brings the received signal to the desired range. The small gain update loop gradually smoothes the received signal to avoid saturation on the AD converter and speedsup convergence of the input

84、 signal level.</p><p>　　Fig. 10. Input/output signal level of digital ampli?er.</p><p>　　8. Conclusions</p><p>　　In this paper, the proposed AGC circuit is designed to adjust the st

85、rength of the received signal to a near constant optimum power level within the dynamic range of various signal processingcomponents in the received signal path. It includes a large gain update loop and a small gain upda

86、te loop to improve convergence speed and at the same time maintain the stability of the AGC circuit. Moreover, it can be used to dynamically control the gain of the received signal with large variations caused by</p&g

87、t;<p>　　References</p><p>　　[1] Heejung Yu et al., IEEE 802.11 wireless LANs ETRI proposal speci?cation for IEEE 802.11 TGn, IEEE 802.11 document, doc. No. 1104092300000n, August, 2004.</p><

88、;p>　　[2] H. Yu, T. Jeon, S. Lee, Design of dualband MIMOOFDM system for next generation wireless LAN, in: IEEE International Conference on Communications (ICC), May, 2005.</p><p>　　[3] V.P.G. Jimenez, M.J

89、.F.G. Garcia, F.J.G. Serrano, A.G. Armada, Design and implementation of synchronization and AGC for OFDMbased WLAN receivers, IEEE Trans. Consum. Electron. 50 (4) (2004) 1016–1025.</p><p>　　[4] A. Fort, W. E