電子專業(yè)畢業(yè)設(shè)計(jì)外文翻譯---關(guān)于直接數(shù)字頻率合成器

1、<p><b>　　畢業(yè)設(shè)計(jì)</b></p><p><b>　?。ㄍ馕姆g材料）</b></p><p>　　All About Direct Digital Synthesis</p><p>　　By Eva Murphy [eva.murphy@analog.com]</p><p&g

2、t;　　Colm Slattery [colm.slattery@analog.com]</p><p>　　What is Direct Digital Synthesis? </p><p>　　Direct digital synthesis (DDS) is a method of producing an analog waveform—usually a sine wave—b

3、y generating a time-varying signal in digital form and then performing a digital-to-analog conversion. Because operations within a DDS device are primarily digital, it can offer fast switching between output frequencies,

4、 fine frequency resolution, and operation over a broad spectrum of frequencies. With advances in design and process technology, today’s DDS devices are very compact and draw little pow</p><p>　　Why would one

5、 use a direct digital synthesizer (DDS)? Aren’t there other methods for easily generating frequencies? </p><p>　　The ability to accurately produce and control waveforms of various frequencies and profiles ha

6、s become a key requirement common to a number of industries. Whether providing agile sources of low-phase-noise variable-frequencies with good spurious performance for communications, or simply generating a frequency sti

7、mulus in industrial or biomedical test equipment applications, convenience, compactness, and low cost are important design considerations. </p><p>　　Figure 1. The AD9833-a one-chip waveform generator.</p&

8、gt;<p>　　Many possibilities for frequency generation are open to a designer, ranging from phase-locked-loop (PLL)-based techniques for very high-frequency synthesis, to dynamic programming of digital-to-analog con

9、verter (DAC) outputs to generate arbitrary waveforms at lower frequencies. But the DDS technique is rapidly gaining acceptance for solving frequency- (or waveform) generation requirements in both communications and indus

10、trial applications because single-chip IC devices can generate programmable </p><p>　　Furthermore, the continual improvements in both process technolog y and design have resulted in cost and power consumptio

11、n levels that were previously unthinkably low. For example, the AD9833, a DDS-based programmable waveform generator (Figure 1), operating at 5.5 V with a 25-MHz clock, consumes a maximum power of 30 milliwatts.</p>

12、<p>　　What are the main benefits of using a DDS? </p><p>　　DDS devices like the AD9833 are programmed through a high speed serial peripheral-interface (SPI), and need only an external clock to generat

13、e simple sine waves. DDS devices are now available that can generate frequencies from less than 1 Hz up to 400 MHz (based on a 1-GHz clock). The benefits of their low power, low cost, and single small package, combined w

14、ith their inherent excellent performance and the ability to digitally program (and re-program) the output waveform, make DDS devices an ext</p><p>　　What kind of outputs can I generate with a typical DDS dev

15、ice? </p><p>　　Figure 2. Square-, triangular-, and sinusoidal outputs from a DDS.</p><p>　　DDS devices are not limited to purely sinusoidal outputs. Figure 2 shows the square-, triangular-, and

16、sinusoidal outputs available from an AD9833.</p><p>　　How does a DDS device create a sine wave? </p><p>　　Here’s a breakdown of the internal circuitry of a DDS device: its main components are a

17、phase accumulator, a means of phase-to-amplitude conversion (often a sine look-up table), and a DAC. These blocks are represented in Figure 3.</p><p>　　A DDS produces a sine wave at a given frequency. The fr

18、equency depends on two variables, the reference-clock frequency and the binar y number programmed into the frequency register (tuning word). </p><p>　　Figure 3. Components of a direct digital synthesizer.<

19、;/p><p>　　The binary number in the frequency register provides the main input to the phase accumulator. If a sine look-up table is used, the phase accumulator computes a phase (angle) address for the look-up ta

20、ble, which outputs the digital value of amplitude—corresponding to the sine of that phase angle—to the DAC. The DAC, in turn, converts that number to a corresponding value of analog voltage or current. To generate a fixe

21、d-frequency sine wave, a constant value (the phase increment—which is determined</p><p>　　What do you mean by a complete DDS? </p><p>　　The integration of a D/A converter and a DDS onto a single

22、 chip is commonly known as a complete DDS solution, a property common to all DDS devices from ADI. </p><p>　　Let’s talk some more about the phase accumulator. How does it work? </p><p>　　Continu

23、ous-time sinusoidal signals have a repetitive angular phase range of 0 to 2.The digital implementation is no different. The counter’s carry function allows the phase accumulator to act as a phase wheel in the DDS implem

24、entation.</p><p>　　To understand this basic function, visualize the sine-wave oscillation as a vector rotating around a phase circle (see Figure 4). Each designated point on the phase wheel corresponds to th

25、e equivalent point on a cycle of a sine wave. As the vector rotates around the wheel, visualize that the sine of the angle generates a corresponding output sine wave. One revolution of the vector around the phase wheel,

26、at a constant speed, results in one complete cycle of the output sine wave. The phase accumu</p><p>　　The phase accumulator is actually a modulo- M counter that increments its stored number each time it rece

27、ives a clock pulse. The magnitude of the increment is determined by the binary-coded input word (M). This word forms the phase step size between reference-clock updates; it effectively sets how many points to skip around

28、 the phase wheel. The larger the jump size, the faster the phase accumulator overflows and completes its equivalent of a sine-wave cycle. The number of discrete phase points c</p><p><b>　　where: </b

29、></p><p>　　fOUT = output frequency of the DDS </p><p>　　M = binary tuning word </p><p>　　fC = internal reference clock frequency (system clock) </p><p>　　n = length

30、of the phase accumulator, in bits </p><p>　　Changes to the value of M result in immediate and phase-continuous changes in the output frequency. No loop settling time is incurred as in the case of a phase-loc

31、ked loop. </p><p>　　As the output frequency is increased, the number of samples per cycle decreases. Since sampling theory dictates that at least two samples per cycle are required to reconstruct the output

32、waveform, the maximum fundamental output frequency of a DDS is fC/2. However, for practical applications, the output frequency is limited to somewhat less than that, improving the quality of the reconstructed waveform an

33、d permitting filtering on the output. </p><p>　　When generating a constant frequency, the output of the phase accumulator increases linearly, so the analog waveform it generates is inherently a ramp. </p&

34、gt;<p>　　Then how is that linear output translated into a sine wave? </p><p>　　A phase -to - amplitude lookup table is used to convert the phase-accumulator’s instantaneous output value (28 bits for A

35、D9833)—with unneeded less-significant bits eliminated by truncation—into the sine-wave amplitude information that is presented to the (10 -bit) D/A converter. The DDS architecture exploits the symmetrical nature of a sin

36、e wave and utilizes mapping logic to synthesize a complete sine wave from one-quarter-cycle of data from the phase accumulator. The phase-to- amplitude lookup </p><p>　　What are popular uses for DDS? </p&

37、gt;<p>　　Applications currently using DDS-based waveform generation fall into two principal categories: Designers of communications systems requiring agile (i.e., immediately responding) frequency sources with exc

38、ellent phase noise and low spurious performance often choose DDS for its combination of spectral performance and frequency-tuning resolution. Such applications include using a DDS for modulation, as a reference for a PLL

39、 to enhance overall frequency tunability, as a local oscillator (LO), or eve</p><p>　　Alternatively, many industrial and biomedical applications use a DDS as a programmable waveform generator. Because a DDS

40、is digitally programmable, the phase and frequency of a waveform can be easily adjusted without the need to change the external components that would normally need to be changed when using traditional analog-programmed w

41、aveform generators. DDS permits simple adjustments of frequency in real time to locate resonant frequencies or compensate for temperature drift. Suchapplicatio</p><p>　　What do you consider to be the key adv

42、antages of DDS to designers of real-world equipment and systems? </p><p>　　Today’s cost- competitive, high - performance, functionally integrated DDS ICs are becoming common in both communication systems an

43、d sensor applications. The advantages that make them attractive to design engineers include: </p><p>　　? digitally controlled micro-hertz frequency-tuning and sub-degree phase-tuning capability, </p>

44、<p>　　? extremely fast hopping speed in tuning output frequency (or phase); phase - continuous frequency hops with no overshoot/undershoot or analog-related loop settling-time anomalies, </p><p>　　? the

45、 digital architecture of DDS eliminates the need for the manual tuning and tweaking related to component aging and temperature drift in analog synthesizer solutions, and </p><p>　　? the digital control inter

46、face of the DDS architecture facilitates an environment where systems can be remotely controlled and optimized with high resolution under processor control. </p><p>　　How would I use a DDS device for FSK enc

47、oding? </p><p>　　Binary frequency-shift keying (usually referred to simply as FSK) is one of the simplest forms of data encoding. The data is transmitted by shifting the frequency of a continuous carrier to

48、one of two discrete frequencies (hence binary). One frequency, f1, (perhaps the higher) is designated as the mark frequency (binary one) and the other, f0, as the space frequency (binary zero). Figure 6 shows an example

49、of the relationship between the mark-space data and the transmitted signal.</p><p>　　This encoding scheme is easily implemented using a DDS. The DDS frequency tuning word, representing the output frequencies

50、, is set to the appropriate values to generate f0 and f1 as they occur in the pattern of 0s and 1s to be transmitted. The user programs the two required tuning words into the device before transmission. In the case of th

51、e AD9834, two frequency registers are available to facilitate convenient FSK encoding. A dedicated pin on the device (FSELECT) accepts the modulating signal a</p><p>　　And how about PSK coding? </p>&

52、lt;p>　　Phase-shift keying (PSK) is another simple form of data encoding. In PSK, the frequency of the carrier remains constant and the phase of the transmitted signal is varied to convey the information. </p>&

53、lt;p>　　Of the schemes to accomplish PSK, the simplest-known as binary PSK (BPSK)—uses just two signal phases, 0 degrees and 180 degrees. BPSK encodes 0 phase shift for a logic 1 input and 180 phase shift for a logic

54、 0 input. The state of each bit is determined according to the state of the preceding bit. If the phase of the wave does not change, the signal state stays the same (low or high). If the phase of the wave reverses (chang

55、es by 180 degrees), then the signal state changes (from low to high, o</p><p>　　PSK encoding is easily implemented with DDS ICs. Most of the devices have a separate input register (a phase register) that can

56、 be loaded with a phase value. This value is directly added to the phase of the carrier without changing its frequency. Changing the contents of this register modulates the phase of the carrier, thus generating a PSK out

57、put signal. For applications that require high speed modulation, the AD9834 allows the preloaded phase registers to be selected using a dedicated togglin</p><p>　　More sophisticated forms of PSK employ four-

58、 or eight- wave phases. This allows binary data to be transmitted at a faster rate per phase change than is possible with BPSK modulation. In four-phase modulation (quadrature PSK or QPSK), the possible phase angles are

59、0, +90, –90, and 180 degrees; each phase shift can represent two signal elements. The AD9830, AD9831, AD9832, and AD9835 provide four phase registers to allow complex phase modulation schemes to be implemented by continu

60、ously updating d</p><p>　　Can multiple DDS devices be synchronized for, say, I-Q capability? </p><p>　　It is possible to use two single DDS devices that operate on the same master clock to outpu

61、t two signals whose phase relationship can then be directly controlled. In Figure 8, two AD9834s are programmed using one reference clock, with the same reset pin being used to update both parts. Using this setup, it is

62、possible to do I-Q modulation.</p><p>　　A reset must be asserted after power-up and prior to transferring any data to the DDS. This sets the DDS output to a known phase, which serves as the common reference

63、point that allows synchronization of multiple DDS devices. When new data is sent simultaneously to multiple DDS units, a coherent phase relationship can be maintained, and their relative phase offset can be predictably s

64、hifted by means of the phase-offset register. The AD9833 and AD9834 have 12 bits of phase resolution, with an eff</p><p>　　What are the key performance specs of a DDS based system?</p><p>　　Phas

65、e noise, jitter, and spurious-free dynamic range (SFDR).</p><p>　　Phase noise is a measure (dBc/Hz) of the short-term frequency instability of the oscillator. It is measured as the single-sideband noise resu

66、lting from changes in frequency (in decibels below the amplitude at the operating frequency of the oscillator using a 1-Hz bandwidth) at two or more frequency displacements from the operating frequency of the oscillator.

67、 This measurement has particular application to performance in the analog communications industry.</p><p>　　Do DDS devices have good phase noise?</p><p>　　Noise in a sampled system depends on ma

68、ny factors. Reference-clock jitter can be seen as phase noise on the fundamental signal in a DDS system; and phase truncation may introduce an error level into the system, depending on the code word chosen. For a ratio t

69、hat can be exactly expressed by a truncated binary-coded word, there is no truncation error. For ratios requiring more bits than are available, the resulting phase noise truncation error results in spurs in a spectral pl

70、ot. Their magnitudes </p><p>　　What about jitter?</p><p>　　Jitter is the dynamic displacement of digital signal edges from their long-term average positions, measured in degrees rms. A perfect o

71、scillator would have rising and falling edges occurring at precisely regular moments in time and would never vary. This, of course, is impossible, as even the best oscillators are constructed from real components with so

72、urces of noise and other imperfections. A high-quality, low-phase-noise crystal oscillator will have jitter of less than 35 picoseconds (ps) of p</p><p>　　Jitter in oscillators is caused by thermal noise, in

73、stabilities in the oscillator electronics, external interference through the power rails, ground, and even the output connections. Other influences include external magnetic or electric fields, such as RF interference fr

74、om nearby transmitters, which can contribute jitter affecting the oscillator’s output. Even a simple amplifier, inverter, or buffer will contribute jitter to a signal.</p><p>　　Thus the output of a DDS devic

75、e will add a certain amount of jitter. Since every clock will already have an intrinsic level of jitter, choosing an oscillator with low jitter is critical to begin with. Dividing down the frequency of a high-frequency c

76、lock is one way to reduce jitter. With frequency division, the same amount of jitter occurs within a longer period, reducing its percentage of system time. </p><p>　　In general, to reduce essential sources o

77、f jitter and avoid introducing additional sources, one should use a stable reference clock, avoid using signals and circuits that slew slowly, and use the highest feasible reference frequency to allow increased oversampl

78、ing. </p><p>　　Spurious-Free Dynamic Range (SFDR) refers to the ratio (measured in decibels) between the highest level of the fundamental signal and the highest level of any spurious, signal—including aliase

79、s and harmonically related frequency components—in the spectrum. For the very best SFDR, it is essential to begin with a high-quality oscillator. </p><p>　　SFDR is an important specification in an applicatio

80、n where the frequency spectrum is being shared with other communication channels and applications. If a transmitter’s output sends spurious signals into other frequency bands, they can corrupt, or interrupt neighboring s

81、ignals. </p><p>　　Typical output plots taken from an AD9834 (10-bit DDS) with a 50MHz master clock are shown in Figure10. In (a), the output frequency is exactly 1/3 of the master clock frequency (MCLK). Bec

82、ause of the judicious choice of frequencies, there are no harmonic frequencies in the 25-MHz window, aliases are minimized, and the spurious behavior appears excellent, with all spurs at least 80 dB below the signal (SFD

83、R = 80 dB). The lower frequency setting in (b) has more points to shape the waveform (but n</p><p>　　(a) fOUT = 16.667MHz (b) fOUT = 4.8MHz.</p><p>　　Figure 10. Output of an

84、AD9834 with a 50MHz master clock</p><p>　　Do you have tools that make it easier to program and predict the performance of the DDS?</p><p>　　The on-line interactive design tool is an assistant fo

85、r selecting tuning words, given a reference clock and desired output frequencies and/or phases. The required frequency is chosen, and idealized output harmonics are shown after an external reconstruction filter has been

86、applied. An example is shown in Figure 11. Tabular data is also provided for the major images and harmonics.</p><p>　　How will these tools help me program the DDS?</p><p>　　All that’s needed is

87、the required frequency output and the system’s reference clock frequency. The design tool will output the full programming sequence required to program the part. In the example in Figure 12, the MCLK is set to 25 MHz and

88、 the desired output frequency is set to 10MHz. Once the update button is pressed, the full programming sequence to program the part is contained in the Init Sequence register.</p><p>　　How can I evaluate you

89、r DDS devices?</p><p>　　All DDS devices have an evaluation board available for purchase. They come with dedicated software, allowing the user to test/evaluate the part easily within minutes of receiving the

90、board. A technical note accompanying each evaluation board contains schematic information and shows best recommended board-design and layout practice.</p><p>　　關(guān)于直接數(shù)字頻率合成器</p><p>　　由伊娃墨菲[eva.mur

91、phy @ analog.com]</p><p>　　寇斯拉特里[colm.slattery @ analog.com]</p><p>　　什么是直接數(shù)字頻率合成器？</p><p>　　直接數(shù)字頻率合成器（DDS）是一種通過產(chǎn)生一個(gè)以數(shù)字形式時(shí)變的信號(hào)，然后執(zhí)行由數(shù)字至模擬轉(zhuǎn)換的方法。由于DDS設(shè)備的操作主要是數(shù)字的，它可以提供快速解決輸出頻率之間切換，優(yōu)點(diǎn)是

92、有精細(xì)的頻率和運(yùn)行頻率范圍廣泛。由于設(shè)計(jì)方面和工藝技術(shù)的進(jìn)步，今天的DDS器件是非常緊湊的小功率。</p><p>　　為什么要使用直接數(shù)字頻率合成器（DDS）？不同頻率和配置文件是不是有其他的方法能夠很容易地產(chǎn)生頻率？</p><p>　　能夠準(zhǔn)確地產(chǎn)生和控制波形已經(jīng)成為一些行業(yè)的主要要求。無論是提供低相位噪聲的雜散性能良好的可變頻率通信，還是只需在生成的頻率上激活工業(yè)或生物醫(yī)學(xué)檢測設(shè)備

93、的應(yīng)用程序，成本低是重要的設(shè)計(jì)考慮。</p><p>　　圖1 AD9833波形發(fā)生器</p><p>　　設(shè)計(jì)師以相位鎖定回路（PLL）為基礎(chǔ)的需要非常高的頻率的合成技術(shù)，以DAC的動(dòng)態(tài)規(guī)劃的數(shù)字toanalog轉(zhuǎn)換器（輸出產(chǎn)生較低的頻率任意波形）來產(chǎn)生許多可能產(chǎn)生的頻率，但DDS技術(shù)迅速獲得了解決頻率（或波形）產(chǎn)生和工業(yè)應(yīng)用要求的方法，因?yàn)閱涡酒呻娐菲骷梢援a(chǎn)生簡單的可編程的模擬

94、輸出高分辨率和準(zhǔn)確性的波形。</p><p>　　此外，在這兩個(gè)過程中不斷改進(jìn)技術(shù)和設(shè)計(jì)，使成本和功耗水平前所未有的低。例如AD9833，一個(gè)基于DDS的可編程波形發(fā)生器（圖1），工作電壓5.5V與25MHz的時(shí)鐘，消耗的最大功率為30mW。</p><p>　　使用DDS有什么主要好處？</p><p>　　對(duì)DDS的AD9833器件進(jìn)行編程，如通過一個(gè)高速串行外

95、設(shè)接口（SPI），而且只需要一個(gè)外部時(shí)鐘來生成簡單的正弦波。DDS器件現(xiàn)已可以產(chǎn)生從1到400MHz的頻率，（時(shí)鐘基于103MHz兆赫）。電源效益低，成本低，包裝單小，加上其固有的優(yōu)良性能，并能夠以數(shù)字形式（和重新編程）輸出波形使DDS器件是極具吸引力的解決方案，相比不太靈活的包括分子聚合離散在內(nèi)的解決方案。</p><p>　　圖2 DDS輸出的矩形波-三角波-正弦波</p><p>　

96、　一個(gè)典型的DDS的設(shè)備可以產(chǎn)出什么樣的輸出？</p><p>　　DDS器件不僅限于純粹的正弦波輸出。圖2顯示了方波、三角波和正弦波輸出。</p><p>　　如何使用DDS的設(shè)備創(chuàng)建一個(gè)正弦波？</p><p>　　圖3 組件的直接數(shù)字合成器</p><p>　　這里有一個(gè)DDS的內(nèi)部電路：其主要成分是相位累加器，振幅轉(zhuǎn)換（通常是正弦查

97、找）和一個(gè)DAC。這些模塊的代表圖如圖3。</p><p>　　DDS產(chǎn)生一個(gè)特定頻率的正弦波。它的頻率取決于兩個(gè)變量，參考時(shí)鐘頻率和（控制字）數(shù)字編程的頻率。</p><p>　　二進(jìn)制數(shù)的頻率主要輸入到相位累加器。在使用正弦查找表時(shí)，用相位累加器計(jì)算一個(gè)階段（角）的地址查找表，輸出幅度的數(shù)字值對(duì)應(yīng)相位角的正弦。反過來，DAC把這個(gè)數(shù)字轉(zhuǎn)換為相應(yīng)值的模擬電壓或電流。要生成一個(gè)固定頻率的正

98、弦波，恒定值（相位增量，這是由二進(jìn)制數(shù)決定）被添加到時(shí)鐘周期的相位累加器。如果相位增量大，相位累加器會(huì)迅速通過正弦查找表，從而產(chǎn)生高頻率的正弦波。如果相位增量小，相位累加器將采取更多的步驟，因而產(chǎn)生較慢的波形。</p><p>　　完整的DDS是什么意思？</p><p>　　D/A轉(zhuǎn)換器和一個(gè)DDS的單一芯片的整合通常被稱為一個(gè)完整的DDS的解決方案，ADI公司的普通性質(zhì)DDS。讓我們說

99、些有關(guān)累加器的知識(shí)。它是如何工作的？連續(xù)時(shí)間正弦信號(hào)的角度范圍內(nèi)有一個(gè)重復(fù)的階段0至2。數(shù)字的實(shí)施沒有什么不同，該計(jì)數(shù)器可以把相位累加器作為DDS的功能來執(zhí)行。</p><p>　　為了理解這一點(diǎn)的基本功能，將可視化的正弦波振蕩作為一個(gè)階段輪圍繞旋轉(zhuǎn)圓向量（見圖4）。每個(gè)階段輪指向?qū)?yīng)的等效點(diǎn)1波周期的正弦。由于矢量旋轉(zhuǎn)的輪子，形象化的角度的正弦值產(chǎn)生相應(yīng)的正弦波。一個(gè)車輪周圍的相速度向量，為一個(gè)常數(shù)，正弦波輸