外文翻譯--版圖中常見的幾個(gè)失效機(jī)制

1、<p><b>　　通信工程學(xué)院</b></p><p><b>　　畢業(yè)生文獻(xiàn)翻譯</b></p><p>　　版圖中常見的幾個(gè)失效機(jī)制</p><p>　學(xué)生姓名：XXX</p><p>　專 業(yè)：微電子</p><p>　班

2、 級(jí)：微電092</p><p>　導(dǎo)師姓名(職稱)：XXX（講師）</p><p>　文獻(xiàn)提交日期：2013年03月01日</p><p>　　版圖中常見的幾個(gè)失效機(jī)制</p><p>　?。ǎ疲幔椋欤酰颍濉　。停澹悖瑁幔睿椋螅恚螅?lt;/p><p>　　Integrated circuits are incredib

3、ly complex devices, and few of them are perfect. Most contain subtle weaknesses and flaws, which predispose them toward eventual failure. Such components can fail catastrophically and without warning after operating perf

4、ectly for many years. Engineers have traditionally relied on quality assurance programs to uncover hidden design flaws. Operation under stressful conditions can accelerate many failure mechanisms, but not every design fl

5、aw can be found by testing.</p><p>　　The designer must therefore find and eliminate as many of these flaws as possible.</p><p>　　The layout of an integrated circuit contributes to many types of

6、failures. If the designer knows about potential weaknesses, then safeguards can be built into the integrated circuit to protect it against failure mechanisms that can be partially or entirely.</p><p>　　Elect

7、rostatic Discharge(ESD)</p><p>　　Almost any form of friction can generate static electricity. For example, if you shuffle across a carpet in dry weather and then touch a metal doorknob, a visible spark will

8、leap from finger to doorknob. The human body acts as a capacitor, and the act of shuffling across a carpet charges this capacitance to a potential of 10000V or more. When a finger is brought near the doorknob, the sudden

9、 discharge creates a visible spark and a perceptible electrical shock. A discharge of less than 50V will d</p><p>　　Proper handing precautions will minimize the risks of electrostatic discharge. ESD-sensitiv

10、e components (including integrated circuits) should always be stored in static-shielded packaging. Grounded wrist straps and soldering irons can reduce potential opportunities for ESD discharges Humidifiers, ionizers, a

11、nd antistaticmats can minimize the buildup of static charges around workstations and machinery. These precautions reduce but do not eliminate ESD damage, so manufacturers routinely include</p><p>　　Special

12、tests can measure the vulnerability of an integrated circuit to ESD. The three most common test configurations are called the human body model(HBM) employs the circuit shown in Figure.</p><p>　　Figure 1 Huma

13、n body model</p><p>　　When the switch is pressed, a 150pF capacitor charged to a specified voltage discharges through a 1.5KΩ series resistor into the device under test(DUT). Ideally, each pair of pins would

14、 be independently tested for ESD susceptibility, but most testing regimens only specify a limited number of pin combinations to reduce test time. Each pair of pins is subjected to a series of positive and negative pulse

15、s; for example, three positive and three negative. After ESD stressing is complete, the part is</p><p>　　Figure shows the circuit employed for the machine model(MM). A 200pF capacitor charged to a specified

16、voltage discharges through a 0.5μH series inductance into the DUT. As in the HBM test, each pin combination is subjected to a predetermined series of positive and negative pulses.with only a small inductance to limit the

17、 peak current, the machine model forms a much harsher test than the human body model. New parts can survive more than 500V under machine model testing.</p><p>　　Figure 2 Machine model</p><p>　　

18、A third ESD test called the charged device model(CDM) is gradually replacing the machine model. The charged device model places the integrated circuit package upside-down on a grounded metal plate and then charges the de

19、vices to a specified voltage through a high-value resistor. A special probe then discharges one pin to a low-impedance ground. Researchers believe that this procedure more accurately model factory handling conditions tha

20、n either the human body or the machine model. CDM testing pr</p><p><b>　　Effects</b></p><p>　　Electrostatic discharge causes several different forms of electrical damage, including d

21、ielectric rupture, dielectric degradation, and avalanche-induced junction leakage. In extreme cases, ESD discharges can even vaporize metallization or shatter the bulk silicon.</p><p>　　Less than 50V will ru

22、pture the gate dielectric of a typical MOS transistor. The rupture occurs in nanoseconds, requires little or no sustained current flow ,and is for all intents and purposes, irreversible. The rupture typically shorts the

23、gate and the back gate of the damaged transistor. Capacitors that use thin insulating dielectrics are also vulnerable to this failure mechanism. An ESD discharge that strikes a pin connecting only to gates or capacitors

24、will usually destroy these devices. If </p><p>　　The integrity of a dielectric can be compromised by an ESD event that does not actually rupture it. The weakened dielectric can fail at any time, perhaps afte

25、r hundreds or thousands of hours of flawless operation.Often the failure dose not occur until the product has been delivered to the customer. Testing cannot screen out this type of delayed ESD failure; instead, vulnerab

26、le dielectrics must be protected against excessive voltages.</p><p>　　Although junctions are considerably more robust than dielectrics, they can still suffer ESD damage. An avalanching junction dumps a large

27、 amount of energy into a small volume of silicon. Extreme current densities can sweep metallization through contacts to short out underlying junctions. Excessive heating can also physically damage junctions by melting or

28、 shattering the silicon. These catastrophic forms of junction damage most often manifest themselves as short circuits. Avalanched junctions tha</p><p>　　Preventative Measures</p><p>　　All vulner

29、able pins must have ESD protection structures connected to their bondpads. Some pins can resist ESD and therefore do not require additional protection. Examples include pins connected to substrate and to large diffusions

30、, such as those found in large power transistors. These large junctions may be also to disperse and absorb the ESD energy before it can damage other circuitry. Pins or devices that can withstand ESD events without the ad

31、dition of ESD protection circuitry are said to be </p><p>　　Pins connecting to relatively small diffusions are vulnerable to ESD-induced junction damage. These junctions are simply not large enough to protec

32、t themselves. Certain junctions, most notably the base-emitter junctions of NPN transistors, are notoriously vulnerable to ESD damage. Avalanching the base-emitter junction of an NPN transistor permanently degrades its

33、beta. A circuit designercan sometimes eliminate the vulnerable junctions by rearranging the circuit. Because ESD vulnerabilities are </p><p>　　Pins that connect only to gates of MOS transistors or to deposi

34、ted capacitor electrodes are extremely vulnerable to ESD damage. Special input protection structures have been developed to protect dielectrics against HBM and MM events. The extremely high currents characteristic of CDM

35、 events require additional protection structures, called CDM clamps, to be placed near the vulnerable devices.</p><p>　　The thin emitter oxides employed in some standard bipolar processes are also susceptibl

36、e to </p><p>　　ESD-induced rupture. This vulnerability can be eliminated by ensuring that leads that connect to external bondpads do not cross any emitter region to which they do not connect. Alternatively,

37、 ESD structures similar to those used for protecting gates can protect the vulnerable circuits. Most modern versions of the standard bipolar process employ thick emitter oxides, which eliminate the need for these precaut

38、ions.</p><p>　　Considerable ingenuity is often required to formulate successful ESD structures for analog integrated circuits. A dozen or more protection circuits are often required to satisfy the large rang

39、e of voltages and the many types of vulnerable devices found in analog circuits. The protection devices must also be evaluated to ensure that they do not interfere with the operation of the circuits they protect. </p&

40、gt;<p>　　The Antenna Effect</p><p>　　Dry etching is known to deposit charges upon the surface of the wafer. Exposed conductors can collect an electrical charge that can damage thin gate dielectrics. T

41、his failure mechanism is called process plasma-induced damage, or, more colorfully , the antenna effect. The antenna effect generates stress-induced leakage currents that can lead to either immediate or delayed failure o

42、f the overstressed dielectrics.</p><p><b>　　Effects</b></p><p>　　The exact source of the electrical charges responsible for the antenna effect is a matter of some controversy. The pl

43、asma itself contains an equal number of positive and negative particles. However, various mechanisms can cause local fluctuations in charge densities due to reactor design and AC plasma excitation, and an effect called e

44、lectron shading, in which adjacent geometries block the isotropic electron flux to a greater degree than they block the anisotropic ion flux. Regardless of the pre</p><p>　　The impact of the antenna effect m

45、ust be evaluated for the etching and ashof each conductor layer. Consider the case of polysilicon. During the initial stages of poly etching the entire surface of the wafer is covered by an unbroken sheet of ploy. Charge

46、 reach this ploy plate through all of the openings in the photoresist. Apparently, the fluctuations responsible for the antenna effect largely cancel one another out across the width of the water,for little damage occurs

47、 at this point. Partway th</p><p>　　During the final stages of photoresist ash, the entire surface of the poly pattern becomes exposed to the plasma. Each geometry now picks up charge across its entire surfa

48、ce and injects this charge through the thin gate oxide. The vulnerability of a given geometry to the antenna effect therefore depends upon the ratio of the total area to the active gate area beneath it. The larger this a

49、real antenna ratio, the greater the risk of plasma-induced damage. Most processes define a maximum allowed ar</p><p>　　Each conductor layer is vulnerable to the antenna effect during etching and ash, so each

50、 layer has its own peripheral and areal antenna ratios. Consider the case of metal-2. Near the end of the etch process, the individual metal-2 geometries become separated from one anther. However, these geometries may be

51、 connected together through lower conductor layers. Therefore, the antenna effect cannot be evaluated on a geometry-by-geometry basis. Instead, one must define collections of electrically conn</p><p>　　A gre

52、at deal of effort has been expended to understand the relationship between antenna ratios and gate dielectric damage, but much remains uncertain. Some researchers have uncovered evidence that PMOS gate oxides are conside

53、rably more sensitive to plasma-induced damage than NMOS gate oxides. Other researchers have shown that oxide isolation greatly reduces plasma-induced damage, presumably by limiting the current that can flow through any g

54、iven area of gate oxide.</p><p>　　Preventative Measures</p><p>　　Any node whose antenna ratio exceeds specifications must be reworked. The exact techniques employed depend upon which layer is in

55、volved. In the case of polysilicon, the ratio can be reduced by inserting metal jumpers. Consider the case shown in Figure. This circuit contains a very long poly lead that crosses a minimum-size MOS transistor M1. The a

56、ntenna ratios of this poly geometry could clearly become very large. If, however, a short metal jumper is inserted in the poly lead next to the transis</p><p><b>　　Figure 3</b></p><p&g

57、t;　　Metal layers are somewhat more difficult to evaluate because metal nodes can connect to diffusions that leak away the charge before it damages gate oxides. For processes that employ gate oxides thicker than about 400

58、?, the source/drain junctions of the MOS transistors will typically avalanche before the gate oxides can be damaged. In such cases, any node that connects to a source/drain diffusion can generally be ignored when computi

59、ng antenna ratios. If a metal node is found to have an excessive</p><p><b>　　Figure 4</b></p><p>　　Leakers for thin-oxide processes are somewhat more problematic. The avalanche volta

60、ge of an NSD/P-epi junction cannot be relied upon to protect a gate oxide much thinner than 400?. Experience has shown that nodes in thin-oxide processes can be protected by a combination of NSD/P-epi and PSD/N-well leak

61、ers. The NSD/P-epi leaker will forward-bias if the node drops below substrate potential. The PSD/N-well leaker will forward-bias if the note rises above the N-well potential, but the reverse-biased</p><p>　　

62、Minority-Carrier Injection</p><p>　　Junction isolation relies on reverse-biased junctions to block unwanted current flow. The electric fields set up by depletion regions repel majority carriers, but they can

63、not block the flow of minority carriers. If any isolation junction forward-biases, it will inject minority carriers into the isolation. Many of these carriers recombine, but some eventually find their way to the depletio

64、n regions isolation other devices.</p><p><b>　　Effects </b></p><p>　　Figure shows a cross section of a standard bipolar circuit. Suppose that the collector of NPN transistor Q1 conne

65、cts to pin of the integrated circuit, and that the external circuitry experiences occasional transient disturbances that pull current out of this pin. If transistor Q1 is off, then these transients pull its tank below gr

66、ound, forward-biasing the collector-substrate junction of Q1 and injecting minority carriers(electrons) into the substrate. Most of these carriers recombine, but some </p><p><b>　　Figure 5</b><

67、;/p><p>　　The transit of minority carriers across the isolation is analogous to the flow of minority carriers through a bipolar transistor. The tank pulled below ground acts as the emitter of lateral NPN transi

68、stor Qp. The isolation and substrate act as the base of this transistor,and any other reverse-biased tank acts as a collector. Each reverse-biased tank forms a separate parasitic transistor corresponding to Qp. The betas

69、 of these parasitic lateral NPN transistors are very low because most of the min</p><p>　　Substrate contacts cannot, by themselves, stop minority-carrier injection , since minority carriers travel by diffusi

70、on and not by drift. Minority carriers are collected only by reverse-biased junctions.However,substrate contacts still provide majority carriers to feed recombination. Since most minority carriers recombine in the isolat

71、ion,substrate contacts remain necessary to prevent substrate biasing.</p><p>　　In some cases, minority-carrier injection can cause a circuit to latch up. Early CMOS processes suffered from a form of this mal

72、ady that has since come to be called CMOS latchup. Figure shows the cross section of a portion of a CMOS die consisting of an NMOS transistor M1 and a PMOS transistor M2. In addition to these two desired MOS transistors,

73、 this layout contains two parasitic bipolar transistors. Lateral NPN transistor Qn, emitter is the source of M1, its base is the isolation, and its coll</p><p><b>　　Figure 6</b></p><p&

74、gt;　　Each transistor then supplies the other's base current. This process becomes self-sustaining if the product of the betas of transistors Qn and Qp exceeds unity. Once this happens, the circuit is said to have lat

75、ched up, and it will remain in this state until power is removed. The integrated circuit can actually conducts so much current that it overheats and self-destructs. Even if this dosenot occur, latchup causes circuit malf

76、unctions and excessive supply current consumption.</p><p>　　CMOS latchup can be triggered in one of two ways. If the source of NMOS transistor M1 is pulled below ground, it will inject minority carriers(elec

77、trons) into the substrate, turning on parasitic transistor Qn. This transistor will then turn on Qp. Alternatively, the source of PMOS transistor M2 may be pulled above the well. It will then inject minority carriers (ho

78、les) into the well and will turn on parasitic transistor Qp. This transistor then turns on Qn. Some authors explain CMOS latchup by c</p><p>　　The obvious way to stop CMOS latchup consists of reducing the be

79、ta of either or both parasitic transistors. If the product of these betas is less than unity, then latchup cannot occur. This is usually achieved by increasing layout spacing, which in turn increases the width of the neu

80、tral base regions of the parasitic lateral transistors. Alternatively, the amount of dopant present in the neutral base region of one(or both) parasitic transistors may be increased. Both of these approaches increase<

81、/p><p>　　Although many CMOS processes claim immunity to latchup, these claims are true only in a somewhat narrow sense. The PNPN structure inherent in such a process lacks sufficient gain to establish regenerat

82、ive feedback, but minority-carrier injection still occurs. The collected carriers can still cause circuit malfunctions, and if positive feedback exists in the circuit, these malfunctions can still cause a for of latchup.

83、 Thesignificance of this observation is frequently underestimated. Any integrat</p><p>　　Preventative Measures (Substrate Injection)</p><p>　　Fundamentally, there are four ways to defeat minorit

84、y-carrier injection: (1) eliminate the forward-biased junctions that cause the problem, (2) increase the spacing between components, (3) increase doping concentrations, and (4) provide alternate collectors to remove unwa

85、nted minority carriers. All of these techniques provide some benefit, and incombination they can correct almost any minority-carrier injection problem.</p><p>　　版圖中常見的幾個(gè)失效機(jī)制</p><p>　?。ǎ疲幔椋欤酰颍濉　。?/p>

86、ｅｃｈａｎｉｓｍｓ）</p><p>　　集成電路是極為復(fù)雜的器件，幾乎不能達(dá)到完美。大多數(shù)器件都存在著微小的不足或缺點(diǎn)，并將最終導(dǎo)致失效。這類期間會(huì)在多年正常工作后突然無法繼續(xù)使用。工程師們通常依靠品質(zhì)保證程序發(fā)現(xiàn)隱藏的設(shè)計(jì)缺陷。在嚴(yán)酷的環(huán)境下工作可加速許多失效機(jī)制，但是并非每個(gè)設(shè)計(jì)缺陷都可通過測(cè)試發(fā)現(xiàn)，因此設(shè)計(jì)者必須盡可能找出并消除這些缺陷。</p><p>　　集成電路版圖會(huì)造成多種

87、類型失效。如果設(shè)計(jì)者了解潛在的薄弱環(huán)節(jié)，那么可以在集成電路中加入保護(hù)措施以防止失效。</p><p>　　靜電泄放（Electrostatic Discharge）</p><p>　　幾乎任何形式的摩擦都會(huì)產(chǎn)生靜電。例如，如果在干燥空氣中拖著腳在地毯上走，然后去摸金屬門，那么在手與門之間會(huì)擦出火花。人體變成電容器，拖著腳在地毯上走可對(duì)人這個(gè)電容器充電到10000V或者更高。當(dāng)手接近門時(shí)，

88、瞬時(shí)的放電就會(huì)產(chǎn)生可見的火花和電擊的感覺。低于50V的放電將毀壞典型集成MOS晶體管的柵介質(zhì)。這樣低的電壓既不會(huì)產(chǎn)生可見的火花，也不會(huì)感覺到電擊。幾乎所有人或機(jī)械行為都可能產(chǎn)生這種低程度的靜電泄放。</p><p>　　適當(dāng)?shù)目刂拼胧┛墒轨o電泄放的風(fēng)險(xiǎn)減至最低。對(duì)ESD敏感器件（包括集成電路）應(yīng)總是存儲(chǔ)于靜電屏蔽包裝中。接地的腕帶和烙鐵可減少潛在的靜電泄放機(jī)會(huì)。加濕器、離化器和抗靜電地毯可減少工作環(huán)境和器械上的靜

89、電荷積累。這些措施可減少但不會(huì)消除ESD損壞，所以制造商無一例外地在集成電路中采用特殊的ESD保護(hù)結(jié)構(gòu)。設(shè)計(jì)這些結(jié)構(gòu)是為了吸收和耗散中等程度的ESD能量而不造成損害。</p><p>　　通過特殊的測(cè)試可測(cè)試出集成電路對(duì)ESD的敏感度。最常見的3種測(cè)試結(jié)構(gòu)稱為人體模型、機(jī)器模型和充電模型。人體模型采用如下圖所示電路。當(dāng)按下開關(guān)，被充電到一定電壓的150pF電容通過1.5KΩ的串聯(lián)電阻向被測(cè)器件放電。理想情況下，應(yīng)

90、單獨(dú)測(cè)試每對(duì)管腳對(duì)ESD的敏感性，但大多數(shù)測(cè)試規(guī)則只指定了有限的管腳組合以節(jié)省測(cè)試時(shí)間。對(duì)每對(duì)管腳加上一連串的正脈沖和負(fù)脈沖，例如，3正3負(fù)。完成對(duì)ESD加壓后，檢測(cè)這部分是否應(yīng)能達(dá)到電性要求。一般認(rèn)為現(xiàn)代集成電路可承受2KV HBM測(cè)試。某些特殊部分管腳要求能承受25KV HBM測(cè)試。</p><p><b>　　圖1 人體模型</b></p><p>　　下圖顯示

91、了采用機(jī)器模型的電路。充電到一定電壓的200pF電容通過0.5μH的串聯(lián)電感向被測(cè)器件放電。和ＨＢＭ測(cè)試相同，每個(gè)管腳組合加上預(yù)先確定的一連串正脈沖和負(fù)脈沖。機(jī)器模型只采用一個(gè)小店干限制峰值電流，構(gòu)成了比人體模型更為嚴(yán)格的測(cè)試。沒有器件能夠在５００Ｖ以上的機(jī)器模型測(cè)試下繼續(xù)使用。</p><p><b>　　機(jī)器模型</b></p><p>　　第三種ＥＳＤ測(cè)試稱為充

92、電器件模型，該模型正在逐漸取代機(jī)器模型。充電器件模型將集成電路封裝上端朝下方在接地的金屬板上，然后通過高值電阻對(duì)器件充電到一定電壓。用特殊探針使一個(gè)管腳對(duì)地阻地放電。研究者相信該過程比人體模型或機(jī)器模型更精確地模擬了工廠操作環(huán)境。ＣＤＭ測(cè)試方法產(chǎn)生了極大電流的短脈沖。典型測(cè)試規(guī)則采用１~１.５ＫＶ的ＣＤＭ測(cè)試。</p><p><b>　　影響</b></p><p>

93、;　　靜電泄放引起幾種不同形式的點(diǎn)損壞，包括介質(zhì)擊穿、介質(zhì)退化和雪崩誘發(fā)結(jié)漏電。在極端情況中，ＥＳＤ放電甚至可以蒸發(fā)金屬層或粉碎體硅。</p><p>　　小于５０Ｖ的電壓可擊穿典型ＭＯＳ晶體管的柵介質(zhì)。擊穿過程只有幾納秒，不需要持續(xù)的電流，并且是不可逆的。擊穿一般使晶體管的柵和被柵短路。采用薄絕緣介質(zhì)的電容也容易出現(xiàn)這種機(jī)制。對(duì)只連接到柵或電容的管腳發(fā)生的ＥＳＤ放電通?？墒蛊骷p壞。如果該管腳還連著擴(kuò)散區(qū)，那么

94、在柵氧化層擊穿前還可能發(fā)生雪崩擊穿。</p><p>　　發(fā)生ＥＳＤ發(fā)電后，可能只對(duì)介質(zhì)完整性有影響并非擊穿。受損的介質(zhì)會(huì)在任意時(shí)刻失效，也許是成千次的正常工作后。這些產(chǎn)品常常在到達(dá)顧客手中發(fā)生失效。測(cè)試不能篩選出這類延遲ＥＳＤ失效；或者說，必須保護(hù)易損介質(zhì)，防止經(jīng)受過大電壓。</p><p>　　盡管結(jié)比介質(zhì)堅(jiān)固的多，但也同樣會(huì)受到ＥＳＤ破壞。雪崩擊穿結(jié)會(huì)向少量硅中傾入大量能量。極大的電

95、流密度可使金屬連線移動(dòng)并穿過接觸，從而使下面的結(jié)短路。過量的熱還可以通過硅熔化或破裂使結(jié)發(fā)生物理變化損壞。這些結(jié)損壞的形式多表現(xiàn)為短路。沒有完全損壞的雪崩結(jié)通常表現(xiàn)為漏電流增大。與過應(yīng)力介質(zhì)不同，損壞結(jié)通常可繼續(xù)工作而不會(huì)進(jìn)一步退化。通常規(guī)定集成電路有遠(yuǎn)大于測(cè)試時(shí)觀察到的漏電流，從而為ＥＳＤ誘發(fā)漏電留有裕量。然而，持續(xù)發(fā)生ＥＳＤ常使結(jié)退化并超出這些寬松的限制。</p><p><b>　　防護(hù)措施<

96、;/b></p><p>　　所有的易損管腳必須有與焊盤連接的ＥＳＤ保護(hù)結(jié)構(gòu)。一些管腳可以抗ＥＳＤ，因此不需要另加保護(hù)。例如與襯底和大擴(kuò)散區(qū)連接的管腳。這種大的結(jié)有能力在ＥＳＤ損壞其他電路之前分散并吸收了能量。不加ＥＳＤ保護(hù)電路而能承受ＥＳＤ事件的管腳和器件成為具有自保功能。</p><p>　　連接到相對(duì)小擴(kuò)散區(qū)的管腳容易出現(xiàn)ＥＳＤ誘發(fā)結(jié)損壞。這類結(jié)只是因?yàn)椴粔虼?，以至于不能進(jìn)行自

97、保護(hù)。某些結(jié)特別易受ＥＳＤ損壞。NPN晶體管發(fā)射結(jié)雪崩擊穿會(huì)永久降低其ß值。電路設(shè)計(jì)者又是通過重新安排電路去掉這種易損壞。因?yàn)镋SD敏感性難以預(yù)測(cè)，因此謹(jǐn)慎的設(shè)計(jì)者會(huì)給所有管腳增加保護(hù)器件，即使某些管腳幾乎不會(huì)受到這種損害。</p><p>　　只與MOS晶體管的柵或淀積電容電極連接的管腳極易受到ESD損害。人們已經(jīng)開發(fā)出特殊的輸入保護(hù)結(jié)構(gòu)，用來保護(hù)介質(zhì)防止發(fā)生HBM和MM事件。CDM事件極高的電流特性

98、需要額外的保護(hù)結(jié)構(gòu)，稱為CDM鉗位，放置在易損器件附近。</p><p>　　某些標(biāo)準(zhǔn)雙級(jí)工藝采用的薄發(fā)射區(qū)氧化層也易發(fā)生ESD誘發(fā)擊穿。保證與外部焊盤相連的金屬線不穿過任何不與之相連的發(fā)射區(qū)可消除這種易受損性?；蛘?，采用與用于保護(hù)柵類似的ESD結(jié)構(gòu)可以保護(hù)這種易受損電路。大多數(shù)現(xiàn)代標(biāo)準(zhǔn)雙極性公藝采用厚的發(fā)射區(qū)氧化層，從而不再需要這些預(yù)防措施。</p><p>　　用于模擬集成電路的成功E