外文翻譯---語(yǔ)言概觀

1、<p>　　附錄4 英文資料及譯文</p><p><b>　　1英文資料</b></p><p>　　(From DIGITAL DESIGN principles & practices ,John F. Wakerly)</p><p>　　Language Overview</p><p>　

2、　What is VHDL?</p><p>　　VHDL is a programming language that has been designed and optimized for describing the behavior of digital systems.</p><p>　　VHDL has many features appropriate for descri

3、bing the behavior of electronic components ranging from simple logic gates to complete microprocessors and custom chips. Features of VHDL allow electrical aspects of circuit behavior (such as rise and fall times of signa

4、ls, delays through gates, and functional operation) to be precisely described. The resulting VHDL simulation models can then be used as building blocks in larger circuits (using schematics, block diagrams or system-level

5、 VHDL descripti</p><p>　　VHDL is also a general-purpose programming language: just as high-level programming languages allow complex design concepts to be expressed as computer programs, VHDL allows the beha

6、vior of complex electronic circuits to be captured into a design system for automatic circuit synthesis or for system simulation. Like Pascal, C and C++, VHDL includes features useful for structured design techniques, an

7、d offers a rich set of control and data representation features. Unlike these other programming la</p><p>　　One of the most important applications of VHDL is to capture the performance specification for a ci

8、rcuit, in the form of what is commonly referred to as a test bench. Test benches are VHDL descriptions of circuit stimuli and corresponding expected outputs that verify the behavior of a circuit over time. Test benches s

9、hould be an integral part of any VHDL project and should be created in tandem with other descriptions of the circuit.</p><p>　　A standard language</p><p>　　One of the most compelling reasons for

10、 you to become experienced with and knowledgeable in VHDL is its adoption as a standard in the electronic design community. Using a standard language such as VHDL virtually guarantees that you will not have to throw away

11、 and recapture design concepts simply because the design entry method you have chosen is not supported in a newer generation of design tools. Using a standard language also means that you are more likely to be able to ta

12、ke advantage of the mo</p><p>　　A brief history of VHDL</p><p>　　VHDL, which stands for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language, was developed in the early 1980s

13、 as a spin-off of a high-speed integrated circuit research project funded by the U.S. Department of Defense. During the VHSIC program, researchers were confronted with the daunting task of describing circuits of enormous

14、 scale (for their time) and of managing very large circuit design problems that involved multiple teams of engineers. With only gate-level design tools</p><p>　　To meet this challenge, a team of engineers fr

15、om three companies ?IBM, Texas Instruments and Intermetrics ?were contracted by the Department of Defense to complete the specification and implementation of a new, language-based design description method. The first pub

16、licly available version of VHDL, version 7.2, was released in 1985. In 1986, the Institute of Electrical and Electronics Engineers, Inc. (IEEE) was presented with a proposal to standardize the language, which it did in 1

17、987 after subs</p><p>　　Although IEEE Standard 1076 defines the complete VHDL language, there are aspects of the language that make it difficult to write completely portable design descriptions (descriptions

18、 that can be simulated identically using different vendors?tools). The problem stems from the fact that VHDL supports many abstract data types, but it does not address the simple problem of characterizing different signa

19、l strengths or commonly used simulation conditions such as unknowns and high-impedance. </p><p>　　Soon after IEEE 1076-1987 was adopted, simulator companies began enhancing VHDL with new, non-standard types

20、to allow their customers to accurately simulate complex electronic circuits. This caused problems because design descriptions entered into one simulator were often incompatible with other simulation environments. VHDL wa

21、s quickly becoming a nonstandard.</p><p>　　To get around the problem of nonstandard data types, another standard was developed by an IEEE committee. This standard, numbered 1164, defines a standard package (

22、a VHDL feature that allows commonly used declarations to be collected into an external library) containing definitions for a standard nine-valued data type. This standard data type is called std_logic, and the IEEE 1164

23、package is often referred to as the Standard Logic package. </p><p>　　The IEEE 1076-1987 and IEEE 1164 standards together form the complete VHDL standard in widest use today. (IEEE 1076-1993 is slowly workin

24、g its way into the VHDL mainstream, but it does not add significant new features for synthesis users.)</p><p>　　Standard 1076.3(often called the Numeric Standard or Synthesis Standard) defines standard packa

25、ges and interpretations for VHDL data types as they relate to actual hardware. This standard, which was released at the end of 1995, is intended to replace the many custom (nonstandard) packages that vendors of synthesis

26、 tools have created and distributed with their products.</p><p>　　IEEE Standard 1076.3 does for synthesis users what IEEE 1164 did for simulation users: increase the power of Standard 1076, while at the same

27、 time ensuring compatibility between different vendors?tools. The 1076.3 standard includes, among other things:</p><p>　　1)   A documented hardware interpretation of values belonging to the bit and

28、 boolean types defined by IEEE Standard 1076, as well as interpretations of the std_ulogic type defined by IEEE Standard 1164.</p><p>　　2)   A function that provides "don&care" or &qu

29、ot;wild card" testing of values based on the std_ulogic type. This is of particular use for synthesis, since it is often helpful to express logic in terms of "don抰 care" values.</p><p>　　3)

30、60;  Definitions for standard signed and unsigned arithmetic data types, along with arithmetic, shift, and type conversion operations for those types.</p><p>　　The annotation of timing information to a

31、simulation model is an important aspect of accurate digital simulation. The VHDL 1076 standard describes a variety of language features that can be used for timing annotation. However, it does not describe a standard met

32、hod for expressing timing data outside of the timing model itself. </p><p>　　The ability to separate the behavioral description of a simulation model from the timing specifications is important for many reas

33、ons. One of the major strengths of Verilog HDL (VHDL抯 closest rival) is the fact that Verilog HDL includes a feature specifically intended for timing annotation. This feature, the Standard Delay Format, or SDF, allows ti

34、ming data to be expressed in a tabular form and included into the Verilog timing model at the time of simulation.</p><p>　　The IEEE 1076.4 standard, published by the IEEE in late 1995, adds this capability t

35、o VHDL as a standard package. A primary impetus behind this standard effort (which was dubbed VITAL, for VHDL Initiative Toward ASIC Libraries) was to make it easier for ASIC vendors and others to generate timing models

36、applicable to both VHDL and Verilog HDL. For this reason, the underlying data formats of IEEE 1076.4 and Verilog SDF are quite similar.</p><p>　　When should you use VHDL?</p><p>　　Why choose to

37、use VHDL for your design efforts? There are many likely reasons. If you ask most VHDL tool vendors this question, the first answer you will get is, "It will improve your productivity." But just what does this m

38、ean? Can you really expect to get your projects done faster using VHDL than by using your existing design methods?</p><p>　　The answer is yes, but probably not the first time you use it, and only if you appl

39、y VHDL in a structured manner. VHDL (like a structured software design language) is most beneficial when you use a structured, top-down approach to design. Real increases in productivity will come later, when you have cl

40、imbed higher on the VHDL learning curve and have accumulated a library of reusable VHDL components. </p><p>　　Productivity increases will also occur when you begin to use VHDL to enhance communication betwee

41、n team members and when you take advantage of the more powerful tools for simulation and design verification that are available. In addition, VHDL allows you to design at a more abstract level. Instead of focusing on a g

42、ate-level implementation, you can address the behavioral function of the design.</p><p>　　How will VHDL increase your productivity? By making it easy to build and use libraries of commonly-used VHDL modules.

43、 VHDL makes design reuse feel natural. As you discover the benefits of reusable code, you will soon find yourself thinking of ways to write your VHDL statements in ways that make them general purpose. Writing portable co

44、de will become an automatic reflex.</p><p>　　Another important reason to use VHDL is the rapid pace of development in electronic design automation (EDA) tools and in target technologies. Using a standard lan

45、guage such as VHDL can greatly improve your chances of moving into more advanced tools (for example, from a basic low-cost simulator to a more advanced one) without having to re-enter your circuit descriptions. Your abil

46、ity to retarget circuits to new types of device targets (for example, ASICs, FPGAs, and complex PLDs) will also be imp</p><p>　　Most of the VHDL features that are needed to support sequential-circuit design,

47、 in particular, processes, were already introduced in section 4.7 and were used in the VHDL sections in chapter 5. This section introduces just a couple more features and gives simple examples of how they are used .Large

48、r examples appear in the VHDL sections of chapter</p><p>　　8. feedback sequential circuits</p><p>　　A VHDL process and the simulator’s event-list mechanism for tracking signal changes form the s

49、equential circuits may change state in response to input changes , and these state changes are manifested by changes propagating in a feedback loop until the feedback loop stabilizes. In simulation, this is manifested by

50、 the simulator putting signal changes on the event list and scheduling processes to return in “delta time” and propagating these signal changes until to no more signal changes are schedu</p><p>　　Table 7-36

51、dataflow VHDL for an S-R latch.</p><p>　　Table 7-36 is a VHDL program for an S-R latch, the architecture contains two concurrent assignment statements. Each of which gives rise to a process, as discussed in

52、section 4.7.9, these processes interact to create the simple latching behavior of a S-R latch.</p><p>　　The VHDL simulation is faithful enough to handle the case where both S and R are asserted simultaneousl

53、y. The most interesting result in simulation occurs if you negate S and R simultaneously. Recall from the box from the page 536 that a real S-R latch may oscillate or go into a metastable state in this simulation. The si

54、mulation will potentially loop forever as each execution of one assignment statement triggers another execution of the other. After some number of repetitions, a well-designed s</p><p>　　WHAT DO ‘U’ WANT<

55、/p><p>　　It would be nice if the S-R latch model in table 7-36 produced a ‘u’ output whenever S and R were negated simultaneously, but it’s not that good. However, the languages is powerful enough that experien

56、ced VHDL designers can easily write a model with that behavior. Such a model would make use of VHDL’s time-modeling facilities, which we haven’t discussed, to model the latch’s “recovery time” (see box in page 537) and f

57、orce a ‘u’ output if a second input change occurred too soon. It’s even possibl</p><p>　　Table 7-37 behavioral VHDL for a positive-edge-triggered D flip-flop</p><p>　　Mote that if a circuit has

58、the possibility of entering a metatable state, there’s no </p><p>　　guarantee that the simulation will detect it, especially in larger designs. The best way to avoid metasbgability problems in a system desig

59、n is to clearly identify and protect its asynchronous boundaries, as discussed in section clocked circuits</p><p>　　In practice, the majority of digital designs that are modeled using VHDL are clocked, synch

60、ronous systems using edge-triggered flip-flops. In addition to what we’ve already learned about VHDL, there’s just one more feature needed to describe edge-triggered behavior. The event attribute attached to a signal nam

61、e to yield a value of type Boolean that is true if an event on the signal caused the encompassing process to run in the current simulation cycle, and false otherwise.</p><p>　　Using the event attribute, we c

62、an model the behavior of a positive-edge-triggered D flip-flop with asynchronous clear as shown in table 7-37. here, the asynchronous clear input CLR overrides any behavior on the clock input CLK and is therefore checked

63、 first, in the “if” clause. If CLR is negated, then the “elsif” clause is checked, and its statements are executed on the rising edge of CLK. Note that “CL’event” is true for any change on CLK, and “CLK=’1’” is checked t

64、o limit triggering to just th</p><p>　　Table 7-38 two more ways to describe a positive-edge-triggered D flip-flop.</p><p>　　In the test bench for a clocked circuit, one of things you need to do

65、is generate a system clock signal. This can be done quite easily with a loop inside a process, as shown in table 7-39 for a 100MHz clock with a 60% duty cycle.</p><p>　　*****SYNTHESIS STUFF*****</p>&

66、lt;p>　　You may be wondering, how does a synthesis tool convert the edge-triggered behavior described in table 7-37 or 7-38 into an efficient flip-flop realization? Most tools recognize only a few predetermined ways of

67、 expressing edge-triggered behavior and map those into predetermined flip-flop components in the target technology.</p><p>　　The synopsis synthesis engine used in the xinlinx foundation series 1.5 software r

68、ecognize the”clk’event and clk=’1’” expression that we use in this book. Even with that as a given, VHDL has many different ways ashenden, author of the designer’s guide to</p><p>　　VHDL (morgan Kaufmann, 19

69、96) ran these statements and one other, with some modification, through several different synthesis tools. Only one of them was able to synthesize three out of the four forms, most could handle only two. So, you need to

70、follow the method that is prescribed by the tool you use. </p><p>　　Table 7-39 clock process within a test bench.</p><p><b>　　reference</b></p><p>　　The problem of metas

71、tability has been around for a long time. Greek philosophers wrote about the problem of indecision thousands of years ago. A group of modem philosophers named Devon sang about metastability in the title song of their Fre

72、edom of choice album. And the u.s. congress still can’t decide how to “save” social security.</p><p>　　Scan capability was first deployed in latches. Not flip-flop, in IBM IC designs decades ago. Edward J.Mc

73、Cluskey has a very good discussion of this and other scan methods in logic design principles (prentice hall, 1986).</p><p>　　Most ASICs and MSI-,PLD- and FPGA-based designs use the sequential circuit types d

74、escribed in this chapter. However , there are other types that are use in both older discrete designs (going all the way back to vacuum-tube logic ) and as well as in modem, custom VLSI designs.</p><p>　　For

75、 example, clocked synchronous state machines are a special case of a more general class of pulse-mode circuits, Such circuits have one or more pulse inputs such that (a) only one pulse occurs at a time; (b) non-pulse inp

76、uts are stable when a pulse occurs; (c) only pulses can cause state changes; and (d) a pulse clock is the single pulse input, and a “pulse” is the triggering edge of the clock. However, it is also possible to build circu

77、its with multiple pulse inputs. These possibilities are d</p><p>　　A particularly important type of pulse-mode circuit that is discussed by McCluskey and others is the two-phase latch machine. The rationale

78、for a two phase clocking approach in VLSI circuits is discussed by Carver Mead and Lynn Conway in introduction to VLSI systems (Addison-Wesley, 1980). There machines essentially eliminate the essential hazards present in

79、 edge-triggered flip-flops by using pairs of latches that are enabled by no overlapping clocks.</p><p>　　Methods for reducing both completely and incompletely specified state tables are described in advanced

80、 logic design texts, including McCluskey’s 1986 book. A more mathematical discussion of these methods and other “theoretical” topics in sequential machine design appears in switching and finite automata theory, second ed

81、ition, by Zvi Kohavi (McFGraw-hall, 1978).</p><p>　　As we showed in this chapter, improperly constructed state diagrams may idle an ambiguous description of next-state behavior. The “if-then-else” structures

82、 in HDLs like ABEL and VHDL can eliminate these ambiguities, but they were not first to do so. Algorithmic-state-machine (ASM) notation. A flowchart-like equivalent of nested if-then-else statement, has been around for o

83、ver 25 years. So-called ASM charts were pioneered at Hewlett-Packard Laboratories by Thomas E. Osborne and were pioneered by </p><p>　　Another notation for describing state machines is an extension of “tradi

84、tional” state-diagram notation called the mnemonic documented state (MDS) diagram. It was developed by William I.Fletcher in an engineering approach to digital design (prentice-hall. 1980). ASM charts and MDS diagrams ha

85、ve now been largely replaced by HDLs and their compilers.</p><p>　　Many CAD environments for digital design include a graphical state diagram entry tool. Unfortunately, these typically support only tradition

86、al state diagrams, making it very easy for a designer to create an ambiguous descriptions of next-state behavior. As a result, my personal recommendation is that you stay away from state-diagram editors and instead use a

87、n HDL to describe your state machines.</p><p>　　We mentioned the importance of synchronizing sequences in connections with state-machine test vectors. There’s actually a very well developed but almost forgot

88、ten theory and practice of synchronizing sequences and somewhat less powerful “homing experiment” described by Frederick C.Hennie in Finite-state Models for logical machines (Wiley, 1968) Unless you’ve got this old class

89、ic on your bookshelf and know how to apply its teachings, please just remember to provide a reset input in every state ma</p><p><b>　　2英文譯文</b></p><p><b>　　語(yǔ)言概觀</b></p

90、><p><b>　　VHDL是什么?</b></p><p>　　VHDL是一種已經(jīng)被為描述成為傳統(tǒng)的行為設(shè)計(jì)最佳化的規(guī)劃語(yǔ)言。</p><p>　　因?yàn)槊枋龇秶鷱暮?jiǎn)單的邏輯門到的電子成份的行為完成微處理器和習(xí)慣規(guī)定， VHDL 讓許多特征適當(dāng)。VHDL的特征允許線路行為 ( 像是上升而且落下時(shí)代的信號(hào)，延遲過(guò)門, 和功能的操作) 的電氣特性精確

91、地被描述。然后在那產(chǎn)生的VHDL 模擬模型為了模擬能在較大的線路 ( 使用圖表, 區(qū)段圖表或系統(tǒng)級(jí)的 VHDL 描述) 中被當(dāng)作建電氣區(qū)段使用。</p><p>　　VHDL 也是一種泛用型的規(guī)劃語(yǔ)言：正如高階層的規(guī)劃語(yǔ)言允許復(fù)雜的要表示成電腦程式的設(shè)計(jì)觀念, VHDL 允許復(fù)雜電子的線路行為對(duì)于自動(dòng)的線路綜合或系統(tǒng)模擬進(jìn)入一個(gè)設(shè)計(jì)系統(tǒng)之內(nèi)被捕獲. 像巴斯卡， C 和 C++, VHDL 包括對(duì)結(jié)構(gòu)化設(shè)計(jì)技術(shù)是有

92、用的, 而且提供一富有組的控制和數(shù)據(jù)表現(xiàn)特征的特征。這些不像其他的規(guī)劃語(yǔ)言， VHDL 提供特征允許協(xié)同的要描述的事件。因?yàn)楸幻枋龉逃械厥褂?VHDL 的硬件在它的操作方面是協(xié)同的，所以這很重要。</p><p>　　VHDL 的最重要申請(qǐng)之一是為一個(gè)線路是以被普遍稱為一張測(cè)試長(zhǎng)椅子的東西形式。測(cè)試長(zhǎng)椅子是線路 stimuli 和隨著時(shí)間的過(guò)去查證線路的行為對(duì)應(yīng)的預(yù)期輸出的 VHDL 描述。測(cè)試長(zhǎng)椅子應(yīng)該是一個(gè)任

93、何 VHDL 計(jì)畫的整體部份并且應(yīng)該在和其他線路的描述前后縱排的馬車中被產(chǎn)生。</p><p><b>　　一種標(biāo)準(zhǔn)的語(yǔ)言</b></p><p>　　你的最無(wú)法抗拒的理由之一是變成的經(jīng)驗(yàn)和聰明的在 VHDL 中是如電子的設(shè)計(jì)一個(gè)標(biāo)準(zhǔn)社區(qū)的它采用。使用一種標(biāo)準(zhǔn)的語(yǔ)言，像是VHDL事實(shí)上保證，只是因?yàn)槟阋呀?jīng)選擇的設(shè)計(jì)進(jìn)入方法不被在比較新的世代設(shè)計(jì)工具中支援，你將不必丟棄

94、，而且取回設(shè)計(jì)觀念。使用一種標(biāo)準(zhǔn)的語(yǔ)言也意味你更可能能夠利用最新設(shè)計(jì)工具而且你將會(huì)有機(jī)會(huì)接近一個(gè)數(shù)以千計(jì)其他的工程師的知識(shí)庫(kù), 他們當(dāng)中的一些人正在解決問(wèn)題的多數(shù)類似你自己的。</p><p>　　VHDL 的簡(jiǎn)短歷史</p><p>　　在1980年代早期內(nèi)代表 VHSIC( 最高速集成電路) 硬件描述語(yǔ)言的 VHDL 被發(fā)展如被美國(guó)國(guó)防部部門贊助的高速集成電路研究計(jì)畫的一個(gè)附帶利益。在

95、 VHSIC 計(jì)劃的時(shí)候，研究員面對(duì)描述巨大尺寸 ( 對(duì)于他們的時(shí)間) 的線路使人畏縮工作并且管理非常大的線路設(shè)計(jì)牽涉了許多工程師團(tuán)隊(duì)的問(wèn)題。由于唯一的門級(jí)設(shè)計(jì)可得的工具, 它很快變成清楚更，比較結(jié)構(gòu)化設(shè)計(jì)方法和工具會(huì)是需要的。</p><p>　　為了要迎接這一挑戰(zhàn), 一些來(lái)自IBM ，德克薩斯工具和 Intermetrics三家公司的工程師被國(guó)防部雇傭完成一個(gè)新的規(guī)格和以語(yǔ)言為基礎(chǔ)的設(shè)計(jì)描述方法。第一 VHD

96、L，7.2 版的公眾可得版本，在 1985到1986年被出版，美國(guó)電氣電子工程師協(xié)會(huì)(IEEE) 與一份提議一起呈現(xiàn)標(biāo)準(zhǔn)化語(yǔ)言，它在提高和修正被做的重要部份之后在 1987 年做被一組由商業(yè)的，政府和學(xué)院的代表組成的成員定義產(chǎn)生了IEEE 1076-1987標(biāo)準(zhǔn), 事實(shí)上這是今天出售的每個(gè)模擬綜合產(chǎn)品的基礎(chǔ)的語(yǔ)言， IEEE 1076-1993 的一個(gè)增強(qiáng)型版本，在1994年出版，而且VHDL工具廠商把這些新的語(yǔ)言特征加入他們的產(chǎn)品以做

97、回應(yīng)。</p><p>　　雖然 IEEE的1076標(biāo)準(zhǔn)定義了完整的VHDL語(yǔ)言, 但是使寫完全手提式的設(shè)計(jì)描述的語(yǔ)言方面是困難的( 能同一地被模擬使用不同的廠商描述硬件工具)。問(wèn)題起源于 VHDL 支持許多摘要數(shù)據(jù)類型，但是它不如未知數(shù)和高阻抗向如此的不同信號(hào)力量或普遍使用過(guò)的模擬所表示簡(jiǎn)單問(wèn)題的特色為條件的運(yùn)行。 </p><p>　　在 IEEE 1076-1987 是采用

98、不久后，模擬器公司開始用新又非標(biāo)準(zhǔn)提高 VHDL 類型允許他們的客戶正確地模擬合成物電子線路。因?yàn)樵O(shè)計(jì)參與一個(gè)模擬器時(shí)常的描述對(duì)其他的模擬環(huán)境不匹配，所以這引起了問(wèn)題. VHDL 正在很快地變成一種非標(biāo)準(zhǔn)的標(biāo)準(zhǔn)。</p><p>　　為了要解決非標(biāo)準(zhǔn)數(shù)據(jù)類型的問(wèn)題, 另外的標(biāo)準(zhǔn)被一個(gè) IEEE 委員會(huì)發(fā)展了。這一個(gè)標(biāo)準(zhǔn)，1164 號(hào), 定義一個(gè)標(biāo)準(zhǔn)的程序包(允許要收集的普遍使用過(guò)的公告進(jìn)入類似一間外部的圖書館之內(nèi)