外文翻譯---stc89c52 數(shù)據(jù)手冊(cè)

1、<p>　　附錄B：外文文獻(xiàn)及譯文</p><p>　　STC89C52 Date Sheet</p><p>　　Description</p><p>　　The STC89C52 is a low-power， high-performance CMOS 8-bit microcontroller with 8K</p><p&g

2、t;　　bytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pinout. The on-

3、chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip， the Atmel S

4、TC89C52 is a powerful microcontroller which provides a highly-fl</p><p>　　The STC89C52 provides the following standard features: 8K bytes of Flash， 256 bytes of RAM， 32 I/O lines， Watchdog timer， two data po

5、inters， three 16-bit timer/counters， a six-vector two-level interrupt architecture， a full duplex serial port， on-chip oscillator， and clock circuitry. In addition， the STC89C52 is designed with static logic for operatio

6、n down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM， timer/counter</p><p><b>　　VCC</b></p><p>　　Suppl

7、y voltage.</p><p><b>　　GND</b></p><p><b>　　Ground.</b></p><p><b>　　Port 0</b></p><p>　　Port 0 is an 8-bit open drain bidirectional I

8、/O port. As an output port， each pin can sink eight TTL inputs. When 1sare written to port 0 pins， the pins can be used as highimpe dance inputs. Port 0 can also be configured to be the multiplexed loworder address/data

9、bus during accesses to external program and data memory. In this mode， P0 has internal pullups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. Externa

10、l pullups are r</p><p><b>　　Port 1</b></p><p>　　Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s ar

11、e written to Port 1 pins， they are pulled high by the internal pullups and can be used as inputs. As inputs， Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. In

12、addition， P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2E</p><p><b>　　Port 2</b></p><p>　　Por

13、t 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins， they are pulled high by the internal pullups and can be used as

14、 inputs. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application， Port 2 uses strong in

15、ternal pull-ups when emitting 1s. During accesses to exte</p><p><b>　　Port 3</b></p><p>　　Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers c

16、an sink/source four TTL inputs. When 1s are written to Port 3 pins， they are pulled high by the internal pullups and can be used as inputs. As inputs， Port 3 pins that are externally being pulled low will source current

17、(IIL) because of the pullups. Port 3 also serves the functions of various special features of the STC89C52， as shown in the following table. Port 3 also receives some control signals for F</p><p><b>　　

18、RST</b></p><p>　　Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 96 oscillator periods after the Watchdog times out. T

19、he DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO， the RESET HIGH out feature is enabled.</p><p><b>　　ALE/PROG</b></p><p&g

20、t;　　Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation

21、， ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes.If desired， ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit se

22、t， ALE is active only during a MOVX or MOVC instruction. Otherwi</p><p><b>　　PSEN</b></p><p>　　Program Store Enable (PSEN) is the read strobe to external program memory. When the STC

23、89C52 is executing code from external program memory， PSEN is activated twice each machine cycle， except that two PSEN activations are skipped during each access to external data memory.</p><p><b>　　EA

24、/VPP</b></p><p>　　External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note， however， tha

25、t if lock bit 1 is programmed， EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash progra

26、mming.</p><p><b>　　XTAL1</b></p><p>　　Input to the inverting oscillator amplifier and input to the internal clock operating circuit.</p><p><b>　　XTAL2</b><

27、;/p><p>　　Output from the inverting oscillator amplifier.</p><p><b>　　譯文：</b></p><p>　　STC89C52 數(shù)據(jù)手冊(cè)</p><p><b>　　功能特性描述</b></p><p>　　S

28、TC89C52是一種低功耗、高性能CMOS8位微控制器，具有8K在系統(tǒng)可編程Flash 存儲(chǔ)器。使用高密度非易失性存儲(chǔ)器技術(shù)制造，與工業(yè)80C51產(chǎn)品指令和引腳完全兼容。片上Flash允許程序存儲(chǔ)器在系統(tǒng)可編程，亦適于常規(guī)編程器。在單芯片上，擁有靈巧的8 位CPU 和在系統(tǒng)可編程Flash，使得STC89C52為眾多嵌入式控制應(yīng)用系統(tǒng)提供高靈活、超有效的解決方案。</p><p>　　STC89C52具有以下標(biāo)

29、準(zhǔn)功能； 8k字節(jié)Flash，256字節(jié)RAM，32 位I/O 口線，看門狗定時(shí)器，2個(gè)數(shù)據(jù)指針，三個(gè)16 位定時(shí)器/計(jì)數(shù)器，一個(gè)6向量2級(jí)中斷結(jié)構(gòu)，全雙工串行口，片內(nèi)晶振及時(shí)鐘電路。另外，STC89C52 可降至0Hz 靜態(tài)邏輯操作，支持2種軟件可選擇節(jié)電模式?？臻e模式下，CPU停止工作，允許RAM、定時(shí)器/計(jì)數(shù)器、串口、中斷繼續(xù)工作。掉電保護(hù)方式下，RAM內(nèi)容被保存，振蕩器被凍結(jié)，單片機(jī)一切工作停止，直到下一個(gè)中斷或硬件復(fù)位為止。&

30、lt;/p><p><b>　　VCC : 電源</b></p><p><b>　　GND: 地</b></p><p>　　P0 口：P0口是一個(gè)8位漏極開路的雙向I/O口。作為輸出口，每位能驅(qū)動(dòng)8個(gè)TTL邏輯電平。對(duì)P0端口寫“1”時(shí)，引腳用作高阻抗輸入。當(dāng)訪問外部程序和數(shù)據(jù)存儲(chǔ)器時(shí)，P0口也被作為低8位地址/數(shù)據(jù)復(fù)用。

31、在這種模式下，P0具有內(nèi)部上拉電阻。在flash編程時(shí)，P0口也用來接收指令字節(jié)；在程序校驗(yàn)時(shí)，輸出指令字節(jié)。程序校驗(yàn)時(shí)，需要外部上拉電阻。</p><p>　　P1 口：P1口是一個(gè)具有內(nèi)部上拉電阻的8 位雙向I/O 口，p1 輸出緩沖器能驅(qū)動(dòng)4個(gè)TTL 邏輯電平。對(duì)P1 端口寫“1”時(shí)，內(nèi)部上拉電阻把端口拉高，此時(shí)可以作為輸入口使用。作為輸入使用時(shí)，被外部拉低的引腳由于內(nèi)部電阻的原因，將輸出電流（IIL）。此

32、外，P1.0和P1.2分別作定時(shí)器/計(jì)數(shù)器2的外部計(jì)數(shù)輸入（P1.0/T2）和時(shí)器/計(jì)數(shù)器2的觸發(fā)輸入（P1.1/T2EX），在flash編程和校驗(yàn)時(shí)，P1口接收低8位地址字節(jié)。</p><p>　　P2 口：P2口是一個(gè)具有內(nèi)部上拉電阻的8 位雙向I/O 口，P2 輸出緩沖器能驅(qū)動(dòng)4個(gè)TTL 邏輯電平。對(duì)P2 端口寫“1”時(shí)，內(nèi)部上拉電阻把端口拉高，此時(shí)可以作為輸入口使用。作為輸入使用時(shí)，被外部拉低的引腳由于內(nèi)

33、部電阻的原因，將輸出電流（IIL）。在訪問外部程序存儲(chǔ)器或用16位地址讀取外部數(shù)據(jù)存儲(chǔ)器（例如執(zhí)行MOVX @DPTR）時(shí)，P2 口送出高八位地址。在這種應(yīng)用中，P2 口使用很強(qiáng)的內(nèi)部上拉發(fā)送1。在使用8位地址（如MOVX @RI）訪問外部數(shù)據(jù)存儲(chǔ)器時(shí)，P2口輸出P2鎖存器的內(nèi)容。在flash編程和校驗(yàn)時(shí)，P2口也接收高8位地址字節(jié)和一些控制信號(hào)。</p><p>　　P3 口：P3 口是一個(gè)具有內(nèi)部上拉電阻的8

34、 位雙向I/O 口，P2 輸出緩沖器能驅(qū)動(dòng)4個(gè)TTL 邏輯電平。對(duì)P3 端口寫“1”時(shí)，內(nèi)部上拉電阻把端口拉高，此時(shí)可以作為輸入口使用。作為輸入使用時(shí)，被外部拉低的引腳由于內(nèi)部電阻的原因，將輸出電流（IIL）。P3口亦作為STC89C52特殊功能（第二功能）使用，如下表所示。在flash編程和校驗(yàn)時(shí)，P3口也接收一些控制信號(hào)</p><p>　　RST: 復(fù)位輸入。晶振工作時(shí)，RST腳持續(xù)2個(gè)機(jī)器周期高電平將使單

35、片機(jī)復(fù)位?？撮T狗計(jì)時(shí)完成后，RST 腳輸出96個(gè)晶振周期的高電平。特殊寄存器AUXR(地址8EH)上的DISRTO位可以使此功能無效。DISRTO默認(rèn)狀態(tài)下，復(fù)位高電平有效。</p><p>　　ALE/PROG：地址鎖存控制信號(hào)（ALE）是訪問外部程序存儲(chǔ)器時(shí)，鎖存低8 位地址的輸出脈沖。在flash編程時(shí)，此引腳（PROG）也用作編程輸入脈沖。在一般情況下，ALE 以晶振六分之一的固定頻率輸出脈沖，可用來作為

36、外部定時(shí)器或時(shí)鐘使用。然而，特別強(qiáng)調(diào)，在每次訪問外部數(shù)據(jù)存儲(chǔ)器時(shí)，ALE脈沖將會(huì)跳過。如果需要，通過將地址為8EH的SFR的第0位置 “1”，ALE操作將無效。這一位置 “1”，ALE 僅在執(zhí)行MOVX 或MOVC指令時(shí)有效。否則，ALE 將被微弱拉高。這個(gè)ALE 使能標(biāo)志位（地址為8EH的SFR的第0位）的設(shè)置對(duì)微控制器處于外部執(zhí)行模式下無效。</p><p>　　PSEN:外部程序存儲(chǔ)器選通信號(hào)（PSEN）是

37、外部程序存儲(chǔ)器選通信號(hào)。當(dāng)STC89C52從外部程序存儲(chǔ)器執(zhí)行外部代碼時(shí)，PSEN在每個(gè)機(jī)器周期被激活兩次，而在訪問外部數(shù)據(jù)存儲(chǔ)器時(shí)，PSEN將不被激活。</p><p>　　EA/VPP:訪問外部程序存儲(chǔ)器控制信號(hào)。為使能從0000H 到FFFFH的外部程序存儲(chǔ)器讀取指令，EA必須接GND。為了執(zhí)行內(nèi)部程序指令，EA應(yīng)該接VCC。在flash編程期間，EA也接收12伏VPP電壓。</p><