外文文獻(xiàn)翻譯--數(shù)據(jù)包處理的硬件支持

1、<p><b>　　中文4130字</b></p><p><b>　?。?lt;/b></p><p>　　二 〇 一 四 年 六 月</p><p>　　Packet Handling Hardware Support </p><p>　　參考文獻(xiàn)：Texas Instrument

2、s.CC1101 Low-Power Sub-1 GHz RF Transceiver.www. ti.com. 2013</p><p>　　The CC1101 has built-in hardware support for packet oriented radio protocols.</p><p>　　In transmit mode, the packet handler

3、 can be configured to add the following elements to the packet stored in the TX FIFO:</p><p>　　A programmable number of preamble bytes</p><p>　　A two byte synchronization (sync) word. Can be dup

4、licated to give a 4-byte sync word (recommended). It is not possible to only insert preamble or only insert a sync word</p><p>　　A CRC checksum computed over the data field.</p><p>　　The recomme

5、nded setting is 4-byte preamble and 4-byte sync word, except for 500 kBaud data rate where the recommended preamble length is 8 bytes. In addition, the following can be implemented on the data field and the optional 2-by

6、te CRC checksum:</p><p>　　Whitening of the data with a PN9 sequence</p><p>　　Forward Error Correction (FEC) by the use of interleaving and coding of the data (convolutional coding)</p>&l

7、t;p>　　In receive mode, the packet handling support will de-construct the data packet by implementing the following (if enabled):</p><p>　　Preamble detection</p><p>　　Sync word detection</p

8、><p>　　CRC computation and CRC check</p><p>　　One byte address check</p><p>　　Packet length check (length byte checked against a programmable maximum length) </p><p>　　De-

9、whitening</p><p>　　De-interleaving and decoding</p><p>　　Optionally, two status bytes (see Table 27 and Table 28) with RSSI value, Link Quality Indication, and CRC status can be appended in the

10、RX FIFO.</p><p>　　Table 27: Received Packet Status Byte 1(first byte appended after the data)</p><p>　　Table 28: Received Packet Status Byte 2(second byte appended after the data)</p><

11、;p>　　1. Data whitening</p><p>　　From a radio perspective, the ideal over the air data are random and DC free. This results in the smoothest power distribution over the occupied bandwidth. This also gives

12、the regulation loops in the receiver uniform operation conditions (on data dependencies).</p><p>　　Real data often contain long sequences of zeros and ones. In these cases, performance can be improved by whi

13、tening the data before transmitting, and de-whitening the data in the receiver.</p><p>　　With CC1101, this can be done automatically. By setting PKTCTRLO. WHITE_DATA=1, all data, except the preamble and the

14、sync word will be XOR-ed with a 9-bit pseudo-random (PN9) sequence before being transmitted. This is shown in Figure 16. At the receiver end, the data are XOR-ed with the same pseudorandom sequence. In this way, the whit

15、ening is reversed, and the original data appear in the receiver. The PN9sequence is initialized to all 1’s.</p><p>　　2. Packet Format </p><p>　　The format of the data packet can be configured an

16、d consists of the following items (see Figure 17):</p><p><b>　　Preamble</b></p><p>　　Synchronization word</p><p>　　Optional length byte</p><p>　　Optional ad

17、dress byte</p><p><b>　　Payload</b></p><p>　　Optional 2 byte CRC</p><p>　　The preamble pattern is an alternating sequence of ones and zeros (10101010…). The minimum lengt

18、h of the preamble is programmable through the value of MDMCFG1.NUM_PREAMBLE. When enabling TX, the modulator will start transmitting the preamble. When the programmed number of preamble bytes has been transmitted, the mo

19、dulator will send the sync word and then data from the TX FIFO if data is available. If the TX FIFO is empty, the modulator will continue ro send preamble bytes until the first byte is</p><p>　　The synchroni

20、zation word is a two-byte value set in the SYNC1 and SYNC0 registers. The sync word provides byte synchronization of the incoming packet. A one-byte sync word can be emulated by setting the AYNC1 value to the preamble pa

21、ttern. It is also possible to emulate a 32 bit sync word by setting MDMCFG2.SYNC_MODE to 3 or 7. The sync word will then be repeated twice.</p><p>　　CC1101 supports both constant packet length protocols and

22、variable length protocols. Variable or fixed packet length mode can be used for packets up to 255 bytes. For longer packets, infinite packet length mode must be used.</p><p>　　Fixed packet length mode is sel

23、ected by setting PKTCTRL0.LENGTH_CONFIG =0. The desired packet length is set by the PKTLEN register. This value must be different from 0.</p><p>　　In variable packet length mode, PKTCTRL0.LENGTH_CONFIG=1, th

24、e packet length is configured by the first byte after the sync word. The packet length is defined as the payload data, excluding the length byte and optional CRC. The PKTLEN register is used to set the maximum packet len

25、gth allowed in RX. Any packet received with a length byte with a value greater than PKTLEN will be discarded. The PKTLEN value must be different from 0. The byte written to the TXFIFO must be different from 0.</p>

26、<p>　　With PKTCTRL0.LENGTH_CONFIG=2, the packet length is set to infinite and transmission and reception will continue until turned off manually. As described in the next section, this can be used to support packet

27、 formats with different length configuration than natively supported by CC1101. one should make sure that TX is not turn off during the transmission of the first half of any byte. Refer to the CC1101 Errata Notes [4] for

28、 more details. </p><p>　　2.1 Arbitrary Length Field Configuration</p><p>　　The packet length register, PKTLEN, can be reprogrammed during receive and transmit. In combination with fixed packet l

29、ength mode (PKTCTRL0. LENGTH_CONFIG=0), this opens the possibility to have a different length field configuration can supported for variable length packets (in variable packet length mode the length byte is the first byt

30、e after the sync word). At the start of reception, the packet length is set a large value. The MCU reads out enough bytes to interpret the length field in the pa</p><p>　　2.2 Packet Length >255</p>

31、<p>　　The packet automation control register, PKTCTRL0, can be reprogrammed during TX and RX. This opens the possibility to transmit and receive packets that are longer than 256 bytes and still be able to use the p

32、acket handling hardware support. At the start of the packet, the infinite packet length mode (PKTCTRL0. LENGTH_CONFIG=2) must be active. On the TX side, the PKTLEN register is set to mod(length, 256). On the RX side the

33、MCU reads out enough bytes to interpret the length field in the packet a</p><p>　　When for example a 600-byte packet is to be transmitted, the MCU should do the following(see also Figure 18)</p><p

34、>　　Set PKTCTRL0.LENGTH_CONFIG=2.</p><p>　　Pre-program the PKTLEN register to mod(600,256)=88.</p><p>　　Transmit at least 345 bytes(600-255), for example by filling the 64-byte TX FIFO six tim

35、es(384 bytes transmitted).</p><p>　　Set PKTCTRL0.LENGTH_CONFIG=0.</p><p>　　The transmission ends when the packet counter reaches 88. a total of 600 bytes are transmitted.</p><p>　　3

36、 Packet filtering in Receive Mode</p><p>　　CC1101 supports three different types of packet-filtering; address filtering, maximum length filtering, and CRC filtering.</p><p>　　3.1 Addressing Filt

37、ering</p><p>　　Setting PKTCTRL1.ADR_CHK to any other value than zero enables the packet address filter. The packet handler engine will compare the destination address byte in the packet with the programmed n

38、ode address in the ADDR register and the 0*00 broadcast address when PKTCTRL1.ADR_CHK=10 or both the 0*00 and 0*FF broadcast addresses when PKTCTRL1.ADR_CHK=11. If the received address matches a valid address, the packet

39、 is received and written into the RX FIFO. If the address match fails, the packet is dis</p><p>　　If the received address matches a valid address when using infinite packet length mode and address filtering

40、is enabled, 0*FF will be written into the RX FIFO followed by the address byte and then the payload data.</p><p>　　3.2Maximum Length Filtering</p><p>　　In variable packet length mode, PKTCTRL0.L

41、ENGTH_CONFIG=1, the PKTLEN.PACKET_LENGTH register value is used to set the maximum allowed packet length. If the received length byte has a larger value than this, the packet is discarded and receive mode restarted(regar

42、dless of the MCSM1.RXOFF_MODE setting).</p><p>　　3.3 CRC Filtering</p><p>　　The filtering of a packet when CRC check fails is enabled by setting PKTCTRL1.CRC_AUTOFLUSH=1. The CRC auto flush func

43、tion will flush the entire RX FIFO if the CRC check fails. After auto flushing the RX FIFO, the next state depends on the MCSM1.RXOFF_MODE setting.</p><p>　　When using the auto flush function, the maximum pa

44、cket length is 63 bytes in variable packet length mode. Note that when PKTCTRL1APPEND_STATUS is enabled, the maximum allowed packet length is reduced by two bytes in order to make room in the RX FIFO for the two status b

45、ytes appended at the end of the packet. Since the entire RX FIFO is flushed when the CRC check fails, the previously received packet must be read out of the FIFO before receiving the current packet. The MCU must not read

46、 from the </p><p>　　4 Packet Handling in Transmit Mode</p><p>　　The payload that is to be transmitted must be written into the TX FIFO. The first byte written must be the length byte when variab

47、le packet length is enabled. The length byte has a value equal to the payload of the packet(including the optional address byte). If address recognition is enabled on the receiver, the second byte written to the TX FIFO

48、must be the address byte.</p><p>　　If fixed packet length is enabled, the first byte written to the TX FIFO should be the address(assuming the receiver uses address recognition).</p><p>　　The mo

49、dulator will first send the programmed number of preamble bytes. If data is avaible in the TX FIFO, the modulator will send the two-bytes(optionally 4-byte) sync word followed by the payload in the TX FIFO. If CRC is ena

50、bled, the checksum is calculated over all the data pulled from the TX FIFO, and the result is sent as two extra bytes following the payload data. If the TX FIFO runs empty before the complete packet has been transmitted,

51、 the radio will enter TXFIFO_UNDERFLOW state. The only</p><p>　　If whitening is enabled, everything following the sync words will be whitened. This is done before the optional FEC/interleaver stage. Whitenin

52、g is enabled by setting PKTCTRL0.WHITE_DATA=1.</p><p>　　If FEC/interleaving is enabled, everything following the sync words will be scrambled by the interleaver and FEC encoded before being modulated. FEC is

53、 enabled by setting MDMCFG1.FEC_EN=1.</p><p>　　5 Packet Handling in Receive Mode</p><p>　　In receive mode, the demodulator and packet handler will search for a valid preamble and the sync word.

54、When found, the synchronism and will receive the first payload byte.</p><p>　　If FEC/interleaving is enabled, the FEC decoder will start to decode the first payload byte. The intrerleaver will de-scramble th

55、e bits before any other processing is done to the data.</p><p>　　If whitening is enabled, the data will be de-whitened at this stage.</p><p>　　When variable packet length mode is enabled, the fi

56、rst byte is the length byte. The packet handler stores this value as the packet length and receives the number of bytes indicated by the length byte. If fixed packet length mode is used, the packet handler will accept th

57、e programmed number of bytes.</p><p>　　Next, the packet handler optionally checks the address and only continues the reception if the address matches. If automatic CRC check is enabled, the packet handler co

58、mputes CRC and matches it with the appended CRC checksum.</p><p>　　At the end of the payload, the packet handler will optionally white two extra packet status bytes(see Table27 and Table28) that contain CRC

59、status, link quality indication, and RSSI value. </p><p>　　6 Packet Handling in Firmware</p><p>　　When implementing a packet oriented radio protocol in firmware, the MCU needs to know when a pac

60、ket has been received/transmitted. Additionally, for packets longer than 64 bytes, the RX FIFO needs to be refilled white in TX. This means that the MCU needs to know the number of bytes that can be read from or written

61、to the RX FIFO and TX FIFO respectively. There are two possible solutions to get the necessary status information:</p><p>　　Interrupt Driven Solution</p><p>　　The GDO pins can be used in both RX

62、 and TX to give an interrupt when a sync word has been received/transmitted or when a complete packet has been received/transmitted by setting IOFGX.GDOx_CFG=0*06. In addition, there are two configurations for the IOCFGx

63、.GDOx_CFG register that can be used as an interrupt source to provide information on how many bytes that are in the RX FIFO and TX FIFO respectively. The IOCFGx.GDOx_CFG=0*02 and IOCFGx.GDOx_CFG=0*03 configurations are a

64、ssociated with the TX FIF</p><p>　　SPI Polling</p><p>　　The PKTSTSTUS register can be polled at a given rate to get information about the current GDO2 and GDO0 values respectively. The RXBYTES a

65、nd TXBYTES registers can be polled at a given rate to get information about the number of bytes in the RX FIFO and TX FIFO respectively. Alternatively, the number of bytes in the RX FIFO and the TX FIFO can be read from

66、the chip status byte returned on the MISO line each time a header byte, data byte, or command strobe is sent on the SPI bus.</p><p>　　It is recommended to employ an interrupt driven solution since high rate

67、SPI polling reduces the RX sensitivity. Furthermore, as explained in Section 10.3 and the CC1101 Errata Notes[4], when using SPI polling, there is a small, but finite, probability that a single read from registers PKSTAT

68、US, RXBYTES and TXBYTES is being corrupt. The same is the case when reading the chip status byte. </p><p>　　Refer to the TI website for SW examples ([9] and [10]). </p><p>　　數(shù)據(jù)包處理的硬件支持</p>

69、<p>　　CC1101 提供了對(duì)數(shù)據(jù)包導(dǎo)向無線協(xié)議的內(nèi)置硬件支持。</p><p>　　在發(fā)送模式下，可對(duì)數(shù)據(jù)包處理器進(jìn)行配置，以添加如下要素到存儲(chǔ)于 TX FIFO內(nèi)的數(shù)據(jù)包中：</p><p>　　一個(gè)可編程前導(dǎo)字節(jié)數(shù)</p><p>　　一個(gè)二字節(jié)（同步）字?？蓪⑵鋸?fù)制以生成一個(gè) 4 字節(jié)同步字（推薦）。不可能只插入前導(dǎo)或者只插入一個(gè)同步字。&

70、lt;/p><p>　　通過數(shù)據(jù)字段計(jì)算的 CRC 校驗(yàn)和。</p><p>　　建議設(shè)置為 4 字節(jié)前導(dǎo)和 4 字節(jié)同步字，建議前導(dǎo)長(zhǎng)度為 8 字節(jié)的 500kBaud 數(shù)據(jù)速率除外。另外，數(shù)據(jù)字段和可選 2 字節(jié) CRC 校驗(yàn)和可執(zhí)行下列操作：</p><p>　　利用 PN9 序列進(jìn)行數(shù)據(jù)白化</p><p>　　通過使用數(shù)據(jù)交錯(cuò)和編碼（卷

71、積碼）實(shí)現(xiàn)前向糾錯(cuò) (FEC)</p><p>　　接收模式下，數(shù)據(jù)包處理支持功能將通過執(zhí)行如下操作（如果已開啟）解析數(shù)據(jù)包：</p><p><b>　　前導(dǎo)檢測(cè)</b></p><p><b>　　同步字檢測(cè)</b></p><p>　　CRC 計(jì)算與 CRC 校驗(yàn)</p><

72、;p><b>　　一字節(jié)地址檢查</b></p><p>　　數(shù)據(jù)包長(zhǎng)度檢查（對(duì)可編程最大長(zhǎng)度進(jìn)行長(zhǎng)度字節(jié)檢查）</p><p><b>　　去白</b></p><p><b>　　去交錯(cuò)與解碼</b></p><p>　　可以選擇將兩個(gè)帶有 RSSI 值、鏈路質(zhì)量指示

73、以及 CRC 狀態(tài)的狀態(tài)字節(jié)（請(qǐng)參見表 27 和表 28）都加入 RX FIFO 中。</p><p>　　表 27 接收數(shù)據(jù)包狀態(tài)字節(jié) 1（數(shù)據(jù)后添加的第一個(gè)字節(jié)）</p><p>　　表 28 接收數(shù)據(jù)包狀態(tài)字節(jié)2（數(shù)據(jù)后添加的第二個(gè)字節(jié)）</p><p><b>　　1 數(shù)據(jù)白化</b></p><p>　　從無線

74、通信角度來看，無線數(shù)據(jù)傳輸?shù)睦硐肭闆r是隨機(jī)和 DC 自由。這就帶來了在占用帶寬上最為均勻的功率分配的問題，同時(shí)也帶來了接收機(jī)統(tǒng)一工作條件下（無數(shù)據(jù)相關(guān)性）的調(diào)節(jié)環(huán)路。</p><p>　　實(shí)際數(shù)據(jù)通常會(huì)包含許多 0 和 1 的長(zhǎng)序列。在這種情況下，通過在發(fā)送以前白化數(shù)據(jù)，以及在接收機(jī)中去白數(shù)據(jù)，便可提高性能。</p><p>　　有了CC1101，這項(xiàng)工作可自動(dòng)地完成。通過設(shè)置PKTCTR

75、L0.WHITE_DATA=1，除前導(dǎo)和同步字以外的所有數(shù)據(jù)在發(fā)送前將通過一個(gè) 9 位偽隨機(jī) (PN9) 序列進(jìn)行異或運(yùn)算，如圖 16 所示。在接收機(jī)端，數(shù)據(jù)由相同的偽隨機(jī)序列進(jìn)行異或運(yùn)算。同樣，將白化數(shù)據(jù)反過來運(yùn)算，便可在接收機(jī)中得到原始數(shù)據(jù)。PN9 序列被全部初始化為 1。</p><p>　　圖 16 TX 模式下的數(shù)據(jù)白化</p><p><b>　　2 數(shù)據(jù)包格式<

76、;/b></p><p>　　可以對(duì)數(shù)據(jù)包格式進(jìn)行配置，其由如下各項(xiàng)組成（請(qǐng)參見圖 17）：</p><p><b>　　前導(dǎo)</b></p><p><b>　　同步字</b></p><p><b>　　可選長(zhǎng)度字節(jié)</b></p><p>&

77、lt;b>　　可選地址字節(jié)</b></p><p><b>　　有效負(fù)載</b></p><p>　　可選 2 字節(jié) CRC</p><p>　　圖 17 數(shù)據(jù)包格式</p><p>　　前導(dǎo)的形式是一個(gè)交互的 0、1 序列（01010101……）。前導(dǎo)的最小長(zhǎng)度是可以通過 MDMCFG1.NUM_PR

78、EAMBLE 的值進(jìn)行編程的。當(dāng)開啟 TX 模式時(shí)，調(diào)制器將開始發(fā)送前導(dǎo)。當(dāng)編程的前導(dǎo)字節(jié)數(shù)被發(fā)送完畢時(shí)，調(diào)制器就開始發(fā)送同步字，然后發(fā)送來自 TX FIFO 的數(shù)據(jù)（如果是有效數(shù)據(jù)的話）。若 TX FIFO 為空，調(diào)制器將繼續(xù)發(fā)送前導(dǎo)字節(jié)，直到第一個(gè)字節(jié)被寫入 TX FIFO 為止。調(diào)制器隨后將發(fā)送同步字，然后發(fā)送數(shù)據(jù)字節(jié)。</p><p>　　同步字是設(shè)置于 SYNC1 和 SYNC0 兩個(gè)寄存器中的 2 字

79、節(jié)值。同步字提供了輸入數(shù)據(jù)包的字節(jié)同步。一個(gè)一字節(jié)同步字可通過設(shè)置前導(dǎo)形式的 SYNC1值來仿真。通過設(shè)置 MDMCFG2.SYNC_MODE=3 或 7 亦可能仿真一個(gè) 32位同步字。該同步字隨后將被重復(fù) 2 次。</p><p>　　CC11001 可支持固定數(shù)據(jù)包長(zhǎng)度協(xié)議和可變數(shù)據(jù)包長(zhǎng)度協(xié)議。可變或固定數(shù)據(jù)包長(zhǎng)度模式可用于長(zhǎng)達(dá) 255 字節(jié)的數(shù)據(jù)包。對(duì)更長(zhǎng)的數(shù)據(jù)包而言，必須使用無長(zhǎng)度限制的數(shù)據(jù)包模式。<

80、;/p><p>　　通過設(shè)置 PKTCTRL0.LENGTH_CONFIG=0，可選擇固定數(shù)據(jù)包長(zhǎng)度模式。理想的數(shù)據(jù)包長(zhǎng)度由 PKTLEN 寄存器來設(shè)置。這個(gè)值必須不同于0。</p><p>　　在可變數(shù)據(jù)包長(zhǎng)度模式下，即 PKTCTRL0.LENGTH_CONFIG=1，通過同步字后面的第一個(gè)字節(jié)來配置數(shù)據(jù)包長(zhǎng)度。數(shù)據(jù)包長(zhǎng)度被定義為有效負(fù)載數(shù)據(jù)，但不包括長(zhǎng)度字節(jié)和可選 CRC。PKTLEN

81、寄存器用于設(shè)置RX 模式中允許的最大數(shù)據(jù)包長(zhǎng)度。任何長(zhǎng)度字節(jié)值大于 PKTLEN 的接收數(shù)據(jù)包將被丟棄。</p><p>　　PKTCTRL0.LENGTH_CONFIG=2 時(shí)，數(shù)據(jù)包長(zhǎng)度設(shè)置為無限，發(fā)送和接收工作將繼續(xù)進(jìn)行，直到手動(dòng)關(guān)閉為止。如下節(jié)所述，其可用于支持那些 CC1100E本不支持的不同長(zhǎng)度配置的數(shù)據(jù)包格式。您應(yīng)該確定，TX 模式在任何字節(jié)前半部分發(fā)送過程中都沒有關(guān)閉。詳情請(qǐng)參見 CC1101 勘

82、誤表說明[4]。</p><p>　　2.1 任意長(zhǎng)度域配置</p><p>　　可在接收和發(fā)送期間對(duì)數(shù)據(jù)包長(zhǎng)度寄存器 PKTLEN 重新編程。結(jié)合固定數(shù)據(jù)包長(zhǎng)度模式 (PKTCTRL0.LENGTH_CONFIG=0)，此舉實(shí)現(xiàn)了支持可變長(zhǎng)度數(shù)據(jù)包以外不同長(zhǎng)度域配置的可能性（在可變包長(zhǎng)度模式下，長(zhǎng)度字節(jié)就是同步字之后的第一個(gè)字節(jié)）。在接收之初，數(shù)據(jù)包長(zhǎng)度設(shè)置為一個(gè)較大的值。MCU 讀出足

83、夠的字節(jié)以解釋數(shù)據(jù)包中的長(zhǎng)度域。然后，根據(jù)這個(gè)值來設(shè)定 PKTLEN 值。當(dāng)數(shù)據(jù)包處理器中的字節(jié)計(jì)數(shù)器相當(dāng)于 PKTLEN 寄存器時(shí)，便到達(dá)了數(shù)據(jù)包的末端。因此，在內(nèi)部計(jì)數(shù)器到達(dá)數(shù)據(jù)包長(zhǎng)度值之前，MCU 必須要能夠編程正確的長(zhǎng)度值。</p><p>　　2.2 數(shù)據(jù)包長(zhǎng)度>255</p><p>　　數(shù)據(jù)包自動(dòng)控制寄存器 PKTCTRL0 可以在 TX 和 RX 模式下完成重新編程，

84、這樣一來就使得發(fā)送和接收長(zhǎng)于 256 字節(jié)的數(shù)據(jù)包成為可能，并且還可以利用數(shù)據(jù)包處理硬件支持。在數(shù)據(jù)包一開始，必須激活無限數(shù)據(jù)包長(zhǎng)度模式(PKTCTRL0.LENGTH_CONFIG=2)。在 TX 端，將 PKTLEN 寄存器設(shè)置為mod (length，256)。在 RX 端，MCU 讀取足夠的字節(jié)以解釋數(shù)據(jù)包中的長(zhǎng)度域，并將 PKTLEN 寄存器設(shè)置為 mod (length，256)。當(dāng)數(shù)據(jù)包剩余字節(jié)少于256 字節(jié)時(shí)，MCU

85、關(guān)閉無限數(shù)據(jù)包長(zhǎng)度模式，并開啟固定數(shù)據(jù)包長(zhǎng)度模式。當(dāng)內(nèi)部字節(jié)計(jì)數(shù)器達(dá)到 PKTLEN 值時(shí)，則發(fā)送或接收終止（無線電設(shè)備進(jìn)入由TXOFF_MODE 或 RXOFF_MODE 決定的狀態(tài)）。另外，還可使用自動(dòng) CRC添加/校驗(yàn)（通過設(shè)置 PKTCTRL0.CRC_EN=1）。</p><p>　　例如，當(dāng)發(fā)送一個(gè) 600 字節(jié)的數(shù)據(jù)包時(shí)，MCU 應(yīng)完成如下步驟：</p><p>　　設(shè)置 P

86、KTCTRL0.LENGTH_CONFIG=2</p><p>　　預(yù)編程 PKTLEN 寄存器為 mod (600，256) = 88</p><p>　　發(fā)送至少 345 字節(jié)（600 – 255），例如填充 64 字節(jié) TX FIFO 六次（發(fā)</p><p>　　送了 384 字節(jié)）。</p><p>　　設(shè)置 PKTCTRL0.LE

87、NGTH_CONFIG=0</p><p>　　數(shù)據(jù)包計(jì)數(shù)器達(dá)到 88 時(shí)結(jié)束發(fā)送?？傆?jì)發(fā)送了 600 字節(jié)。</p><p>　　數(shù)據(jù)包處理器的內(nèi)部字節(jié)計(jì)數(shù)器從 0 計(jì)數(shù)到 255，然后再?gòu)?0 開始計(jì)數(shù)。</p><p>　　圖 18 數(shù)據(jù)包長(zhǎng)度＞255</p><p>　　3 接收模式下的數(shù)據(jù)包濾波</p><p&g

88、t;　　CC1100E 支持三種不同類型的數(shù)據(jù)包濾波：地址濾波，最大長(zhǎng)度濾波，CRC 濾波。</p><p><b>　　3.1 地址濾波</b></p><p>　　設(shè)置 PKTCTRL1.ADR_CHK 為 0 以外的任何值便可開啟數(shù)據(jù)包地址濾波器。該包處理器引擎會(huì)將數(shù)據(jù)包中的目標(biāo)地址字節(jié)與 ADDR 寄存器中的編程節(jié)點(diǎn)地址，以及 PKTCTRL1.ADR_CHK

89、=10 時(shí)的 0x00 廣播地址或者PKTCTRL1.ADR_CHK=11 時(shí)的 0x00 和 0Xff 廣播地址進(jìn)行比較。如果接收到的地址匹配一個(gè)有效地址，則接收該數(shù)據(jù)包，并將其寫入 RX FIFO。如果地址匹配失敗， 則丟棄該數(shù)據(jù)包， 并重新啟動(dòng)接收模式（ 與MCSM1.RXOFF_MODE 設(shè)置無關(guān)）。</p><p>　　使用無限數(shù)據(jù)包長(zhǎng)度模式并且地址濾波開啟時(shí)，如果接收到的地址匹配一個(gè)有效地址，那么 0

90、xFF 便會(huì)被寫入 RX FIFO，之后是地址字節(jié)，最后是有效負(fù)載數(shù)據(jù)。</p><p>　　3.2 最大長(zhǎng)度濾波</p><p>　　在 可 變 數(shù) 據(jù) 包 長(zhǎng) 度 模 式 下 ， 即 PKTCTRL0.LENGTH_CONFIG = 1 ，PKTLEN.PACKET_LENGTH 寄存器值用于設(shè)置最大允許的數(shù)據(jù)包長(zhǎng)度。如果接收到的長(zhǎng)度字節(jié)具有一個(gè)比該允許的長(zhǎng)度更大值，則丟棄該數(shù)據(jù)包，并

91、且重新啟動(dòng)接收模式（與 MCSM1.RXOFF_MODE 設(shè)置無關(guān)）。</p><p>　　3.3 CRC 濾波</p><p>　　如果 CRC 校驗(yàn)失敗，則設(shè)置 PKTCTRL1.CRC_AUTOFLUSH=1 來開啟數(shù)據(jù)包濾波。如果 CRC 校驗(yàn)失敗，CRC 自動(dòng)刷新功能將會(huì)刷新整個(gè) RX FIFO。自動(dòng)刷新 RX FIFO 以后，后面的狀態(tài)則取決于 MCSM1.RXOFF_MODE

92、 的設(shè)置。</p><p>　　當(dāng)使用自動(dòng)刷新功能時(shí)，可變數(shù)據(jù)包長(zhǎng)度模式下的最大數(shù)據(jù)包長(zhǎng)度為 63 字節(jié)，而固定數(shù)據(jù)包長(zhǎng)度模式下則為 64 字節(jié)。請(qǐng)注意， 開啟PKTCTRL1.APPEND_STATUS 之后，最大允許的數(shù)據(jù)包長(zhǎng)度減小 2 字節(jié)，目的是在 RX FIFO 中為數(shù)據(jù)包末尾添加的 2 個(gè)狀態(tài)字節(jié)留出空間。由于 CRC校驗(yàn)失敗時(shí)整個(gè) RX FIFO 被刷新，之前接收到的數(shù)據(jù)包必須在接收當(dāng)前數(shù)據(jù)包以前從

93、 FIFO 讀取出來。在 CRC 校驗(yàn)為 OK 以前，MCU 不能讀取當(dāng)前數(shù)據(jù)包。</p><p>　　4 發(fā)送模式下的數(shù)據(jù)包處理</p><p>　　必須要將即將要被發(fā)送的有效負(fù)載寫入 TX FIFO 中。開啟可變數(shù)據(jù)包長(zhǎng)度以后，長(zhǎng)度字節(jié)必須最先被寫入。長(zhǎng)度字節(jié)具有一個(gè)與數(shù)據(jù)包有效負(fù)載相當(dāng)?shù)闹担ò蛇x地址字節(jié)）。如果接收機(jī)端開啟了地址識(shí)別，則寫入 TX FIFO 的第二個(gè)字節(jié)必須為地址

94、字節(jié)。如果開啟了固定數(shù)據(jù)包長(zhǎng)度，則寫入 TX FIFO 的第一個(gè)字節(jié)應(yīng)為地址字節(jié)（假設(shè)接收機(jī)使用了地址識(shí)別）。</p><p>　　調(diào)制器會(huì)首先發(fā)送編程的前導(dǎo)字節(jié)數(shù)。如果 TX FIFO 中的數(shù)據(jù)可用，則調(diào)制器會(huì)發(fā)送 2 字節(jié)（可選 4 字節(jié)）同步字，之后是 TX FIFO 中的有效負(fù)載。如果開啟了 CRC，則在所有取自 TX FIFO 的數(shù)據(jù)上計(jì)算校驗(yàn)和，并在有效負(fù)載之后以 2 個(gè)額外字節(jié)發(fā)送該結(jié)果。如果 TX

95、 FIFO 在發(fā)送完全部數(shù)據(jù)包以前變?yōu)榭?，那么該無線電設(shè)備將進(jìn)入 TXFIFO_UNDERFLOW 狀態(tài)。退出該狀態(tài)的唯一方法是發(fā)出一個(gè) SFTX 選通脈沖。</p><p>　　在出現(xiàn)下溢以后對(duì) TX FIFO 進(jìn)行寫操作并不會(huì)重啟 TX 模式。</p><p>　　如果開啟了數(shù)據(jù)白化功能，則同步字之后的所有數(shù)據(jù)將被白化。這一工作在可選FEC/交錯(cuò)以前便完成?？蓪?PKTCTRL0.WH

96、ITE_DATA 設(shè)置為 1 來開啟數(shù)據(jù)白化功能。</p><p>　　如果開啟了 FEC/交錯(cuò)，同步字之后的所有數(shù)據(jù)將被調(diào)制以前編碼的交錯(cuò)和</p><p>　　FEC 加密編碼。將 MDMCFG1.FEC_EN 設(shè)置為 1 便可開啟 FEC。</p><p>　　5 接收模式下的數(shù)據(jù)包處理</p><p>　　在接收模式下，解調(diào)器和數(shù)據(jù)包

97、處理器將會(huì)搜索一個(gè)有效的前導(dǎo)和同步字。如果找到，解調(diào)器就獲得了位和字節(jié)同步機(jī)制，并將接收第一個(gè)有效負(fù)載字節(jié)。若 FEC/交錯(cuò)開啟，則 FEC 解碼器將開始對(duì)第一個(gè)有效負(fù)載字節(jié)進(jìn)行解碼。交錯(cuò)器將在任何其他數(shù)據(jù)處理過程之前對(duì)這些位進(jìn)行解密。</p><p>　　如果白化功能開啟了，則在這個(gè)階段數(shù)據(jù)將被去白。</p><p>　　當(dāng)可變數(shù)據(jù)包長(zhǎng)度模式開啟時(shí)，則第一個(gè)字節(jié)為長(zhǎng)度字節(jié)。數(shù)據(jù)包處理器把

98、這個(gè)值作為數(shù)據(jù)包長(zhǎng)度存儲(chǔ)，并接收該長(zhǎng)度字節(jié)顯示數(shù)目的字節(jié)。如果使用了固定數(shù)據(jù)包長(zhǎng)度模式，則數(shù)據(jù)包處理器將會(huì)接受編程數(shù)目的字節(jié)。</p><p>　　接下來，數(shù)據(jù)包處理器隨意地校驗(yàn)地址，并在地址匹配時(shí)才繼續(xù)進(jìn)行接收。若自動(dòng) CRC 校驗(yàn)開啟，則數(shù)據(jù)包處理器會(huì)計(jì)算 CRC，并將其與附加 CRC 校驗(yàn)和相匹配。</p><p>　　在有效負(fù)載末端，數(shù)據(jù)包處理器將隨意寫入 2 個(gè)包含 CRC 狀態(tài)

99、、鏈路質(zhì)量指示和 RSSI 值的額外數(shù)據(jù)包狀態(tài)字節(jié)（請(qǐng)參見表 25 和表 26）。</p><p>　　6 固件中的數(shù)據(jù)包處理</p><p>　　在固件中執(zhí)行數(shù)據(jù)包導(dǎo)向無線協(xié)議時(shí)，MCU 需要知道一個(gè)數(shù)據(jù)包何時(shí)被接收到/發(fā)送出去。另外，數(shù)據(jù)包長(zhǎng)度大于 64 字節(jié)時(shí)，需要在 RX 模式下讀取 RXFIFO，需要在 TX 模式下重填 TX FIFO。這就是說，MCU 需要知道能夠?qū)懭隦X F

100、IFO 和 TX FIFO 或從 RX FIFO 和 TX FIFO 讀取的字節(jié)。獲得該必要狀態(tài)信息的解決方案有如下兩種：</p><p><b>　　a) 中斷驅(qū)動(dòng)法</b></p><p>　　當(dāng)通過設(shè)置 IOCFGx.GDOx_CFG=0x06 接收到/發(fā)送出一個(gè)同步字或接收到/發(fā)送出一個(gè)完整數(shù)據(jù)包時(shí)，在 RX 和 TX 模式下均可使用 GDO 引腳來實(shí)現(xiàn)中斷。

101、另外，IOCFGx.GDOx_CFG 寄存器具有兩種配置，可用作中斷源，從而提供 RX FIFO 和 TX FIFO 中分別有多少個(gè)字節(jié)的相關(guān)信息。</p><p>　　IOCFGx.GDOx_CFG=0x00 和 IOCFGx.GDOx_CFG=0x01 兩種配置與 RXFIFO 相關(guān)，而 IOCFGx.GDOx_CFG=0x02 和 IOCFGx.GDOx_CFG=0x03 則與 TX FIFO 相關(guān)。<

102、;/p><p><b>　　b) SPI 輪詢</b></p><p>　　可以某個(gè)給定速率對(duì) PKTSTATUS 寄存器輪詢，以獲取 GDO2 和 GDO0 當(dāng)前值的相關(guān)信息?？梢阅硞€(gè)給定速率對(duì) RXBYTES 和 TXBYTES 寄存器輪詢，以獲取 RX FIFO 和 TX FIFO 中所含字節(jié)數(shù)的相關(guān)信息。另外，在 SPI 總線上每發(fā)送一個(gè)報(bào)頭字節(jié)、數(shù)據(jù)字節(jié)或指令選

103、通脈沖時(shí)，可從 MISO 線路上返回的芯片狀態(tài)字節(jié)讀取到 RX FIFO 和 TX FIFO 中所含的字節(jié)數(shù)。</p><p>　　推薦使用中斷驅(qū)動(dòng)方法，因?yàn)楦咚?SPI 輪詢可降低 RX 靈敏度。而且，如章節(jié)10.3 及《CC1100E 勘誤表說明》[5] 所述，當(dāng)使用 SPI 輪詢時(shí)，存在一定的概率（雖然這種概率較低）：?jiǎn)巫止?jié)讀取寄存器 PKTSTATUS、RXBYTES 和TXBYTES 將會(huì)失敗。讀取芯片