led畢業(yè)設(shè)計(jì)外文翻譯

1、<p><b>　　外文資料翻譯</b></p><p>　　LED using digital tube digital display its high-brightness, indicating the advantages of intuitive intelligence is widely used in areas such as equipment and hou

2、sehold appliances. AT89C52This article describes a single-chip microcomputer as the core, to a total of anode high-brightness LED L ED as a display composed of seven figures show that the practical design of multi-functi

3、on electronic clocks, the clock shows a week, hour, minute, second, it can be switched to year, month, day showed that </p><p>　　Clock circuit is the heart of the computer, which controls the rhythm of the w

4、ork of the computer is through the completion of complex sequential circuits function in different directions.</p><p>　　Clock, since it was invented that day on, people's lives has become an indispensabl

5、e tool, especially in this era of efficient, the clock is in the human production and living, learning and other fields is widely. However, with the passage of time, people not only to the requirements of the clock is ge

6、tting higher and higher precision, and functional requirements for the clock more and more, the clock has not only a tool used to display time, in many practical applications It also needs to be ab</p><p>　　

7、With the development of human civilization, science and technology, there is the request of the clock continues to improve. Clock has not only seen as a tool to display the time, in many practical applications also need

8、to be able to achieve more other functions. High-precision, multifunction, small size, low power consumption, is the development trend of the modern clock. In this trend, digital clock, multifunction clock has become the

9、 modern design of the production of research-led direction. </p><p>　　The design is based on the principle of single-chip technology to chip AT89C52single-chip microcomputer as the core controller, through t

10、he production of hardware and software procedures for the preparation, design to produce a multi-functional digital clock system. The clock system mainly by clock module, alarm module, the ambient temperature detection m

11、odule, liquid crystal display module, control module and the keyboard signal prompted module. System is simple and clear user interface that ca</p><p>　　Clock design is no theory of discrete logic, programma

12、ble logic, or using full-custom silicon devices of any digital design, in order to successfully operate and reliable clock is crucial. Poor design of the clock in the limits of temperature, voltage deviation or the manuf

13、acturing process will result in the case wrong, and debugging difficult, spending a lot. In the design of FPGA / CPLD clock when several types of commonly used. Clock can be divided into the following four types: global

14、clock,</p><p>　　No matter what methods are the real circuit clock tree can not achieve the ideal assumption that the clock, so we must be based on an ideal clock, the clock real work to build a model to anal

15、yze the circuit, so as to make the circuit performance and the practical work as expected . Clock in the actual model, we have to consider the spread of clock-tree skew, vertical jump and absolute bias and other uncertai

16、nties. </p><p>　　To register, the clock was working along the arrival of the data terminal when it should have been stable, so as to ensure that the work along the sampling clock to the accuracy of the data,

17、 this data preparation time that we call set-up time (setup time). Data should also be working along the clock to maintain over a period of time, this period of time known as the hold time (hold time). </p><p&

18、gt;　　Global clock for a design project, the global clock (or clock synchronous) is the simplest and most predictable clock. In the PLD / FPGA design of the clock the best options are: by a dedicated global clock input pi

19、ns of a single master clock-driven clock design projects to each flip-flop. As long as possible should be used in the design of global clock projects. PLD / FPGA has a dedicated global clock pins, the device is directly

20、connected to each register. Global clock to provide such a device</p><p>　　Clock-gated in many applications, the entire design of the overall use of external clock is not possible or practical. With the prod

21、uct of PLD logic array clock (that is, the clock is generated by the logic), to allow arbitrary function alone all trigger clock. However, when you use the array clock, the clock should be carefully analyzed the function

22、, in order to avoid glitches. </p><p>　　Usually constitute the array clock clock-gated. Clock gating often interface with the microprocessor, and used the address to write to control the pulse line. However,

23、 when using combination of flip-flop when the clock function, usually there is a clock-gated. If the following conditions, such as clock gating can be as reliable as global clock work: </p><p>　　Drive the cl

24、ock logic must contain only one "and" the door or a "or" gate. If any additional work in some state of logic, the competition will be the burr. </p><p>　　A logic gate input as the actual

25、clock, and the logic gate must be of all other input as the address or control lines, in relation to their compliance with the establishment and maintenance of clock time bound. </p><p>　　Multi-level logic g

26、enerated clock when the clock-gating logic of the combination of more than one (or more than the individual "and" doors or "or" gate), the evidence of the reliability of the design of the project has

27、become very difficult. Even if the prototype or simulation results show that there is no static dangerous, but in fact the risk may still exist. In general, we should not use multi-level combinational logic to clock the

28、flip-flop in the PLD design. </p><p>　　Traveling-wave clock clock another popular use of traveling-wave circuit is the clock, that is, the output of a flip-flop used as a clock input of another flip-flop. If

29、 careful design, traveling-wave clock can be the same as the global clock to work reliably. However, the traveling-wave clock made from time to time with the calculation of the circuit becomes very complicated. Line-wave

30、 traveling-wave clock flip-flop of the chain have a greater clock time between the offset and exceed the worst c</p><p>　　Multi-clock system, many system requirements within the same multi-PLD clock. The mos

31、t common example is the two asynchronous interfaces between microprocessors, or microprocessors and asynchronous communication channel interface. As the clock signal between the two requirements to establish and maintain

32、 a certain time, so that the above application from time to time the introduction of additional constraints. They also requested that some asynchronous synchronization signal. </p><p>　　In many applications,

33、 only the synchronization of asynchronous signals is not enough, when the system of two or more non-homologous clock, the data it is difficult to establish and maintain the time to be assured that we will face the comple

34、x matter of time . The best way is to all non-homologous clock synchronization. PLD internal use of the lock loop (PLL or DLL) is a very good, but not all of PLD with a PLL, DLL, and chip PLL with most expensive, so unle

35、ss there are special requirements, the </p><p>　　采用L ED 數(shù)碼管的數(shù)字顯示以其亮度高、顯示直觀等優(yōu)點(diǎn)被廣泛應(yīng)用于智能儀器及家用電器等領(lǐng)域. 本文介紹一種以AT89C52單片機(jī)為核心,以共陽極高亮度L ED 數(shù)碼管作為顯示器件組成7 位數(shù)字顯示的實(shí)用多功能電子時(shí)鐘的設(shè)計(jì),該時(shí)鐘可顯示星期、時(shí)、分、秒,也可切換為年、月、日顯示,同時(shí)具有整點(diǎn)音樂報(bào)時(shí)及定時(shí)鬧鐘等功

36、能,也可作電子秒表使用。</p><p>　　時(shí)鐘電路是計(jì)算機(jī)的心臟, 它控制著計(jì)算機(jī)的工作節(jié)奏就是通過復(fù)雜的時(shí)序電路完成不同的指令功能的。</p><p>　　時(shí)鐘，自從它被發(fā)明的那天起，就成為人們生活中必不可少的一種工具，尤其是在現(xiàn)在這個(gè)講究效率的年代，時(shí)鐘更是在人類生產(chǎn)、生活、學(xué)習(xí)等多個(gè)領(lǐng)域得到廣泛的應(yīng)用。然而隨著時(shí)間的推移，人們不僅對于時(shí)鐘精度的要求越來越高，而且對于時(shí)鐘功能的要求

37、也越來越多，時(shí)鐘已不僅僅是一種用來顯示時(shí)間的工具，在很多實(shí)際應(yīng)用中它還需要能夠?qū)崿F(xiàn)更多其它的功能。諸如鬧鐘功能、日歷顯示功能、溫度測量功能、濕度測量功能、電壓測量功能、頻率測量功能、過欠壓報(bào)警功能等。鐘表的數(shù)字化給人們的生產(chǎn)生活帶來了極大的方便，而且大大地?cái)U(kuò)展了鐘表原先的報(bào)時(shí)功能。諸如定時(shí)自動(dòng)報(bào)警、按時(shí)自動(dòng)打鈴、時(shí)間程序自動(dòng)控制、定時(shí)廣播、自動(dòng)起閉路燈、定時(shí)開關(guān)烘箱、通斷動(dòng)力設(shè)備、甚至各種定時(shí)電氣的自動(dòng)啟用等，所有這些，都是以鐘表數(shù)字化

38、為基礎(chǔ)的。可以說，設(shè)計(jì)多功能數(shù)字時(shí)鐘的意義已不只在于數(shù)字時(shí)鐘本身，更大的意義在于多功能數(shù)字時(shí)鐘在許多實(shí)時(shí)控制系統(tǒng)中的應(yīng)用。在很多實(shí)際應(yīng)用中，只要對數(shù)字時(shí)鐘的程序和硬件電路加以一定的修改，便可以得到實(shí)時(shí)控制的實(shí)用系統(tǒng)，從而應(yīng)用到實(shí)際工作與生產(chǎn)中去。因此，研究數(shù)字時(shí)鐘及擴(kuò)大其應(yīng)用，有著非?，F(xiàn)實(shí)的意義。</p><p>　　隨著人類科技文明的發(fā)展，人們對于時(shí)鐘的要求在不斷地提高。時(shí)鐘已不僅僅被看成一種用來顯示時(shí)間的工具

39、，在很多實(shí)際應(yīng)用中它還需要能夠?qū)崿F(xiàn)更多其它的功能。高精度、多功能、小體積、低功耗，是現(xiàn)代時(shí)鐘發(fā)展的趨勢。在這種趨勢下，時(shí)鐘的數(shù)字化、多功能化已經(jīng)成為現(xiàn)代時(shí)鐘生產(chǎn)研究的主導(dǎo)設(shè)計(jì)方向。本文正是基于這種設(shè)計(jì)方向，以單片機(jī)為控制核心，設(shè)計(jì)制作一個(gè)符合指標(biāo)要求的多功能數(shù)字時(shí)鐘。</p><p>　　本設(shè)計(jì)基于單片機(jī)技術(shù)原理，以單片機(jī)芯片AT89C52作為核心控制器，通過硬件電路的制作以及軟件程序的編制，設(shè)計(jì)制作出一個(gè)多功能

40、數(shù)字時(shí)鐘系統(tǒng)。該時(shí)鐘系統(tǒng)主要由時(shí)鐘模塊、鬧鐘模塊、環(huán)境溫度檢測模塊、液晶顯示模塊、鍵盤控制模塊以及信號提示模塊組成。系統(tǒng)具有簡單清晰的操作界面，能在4V～7V直流電源下正常工作。能夠準(zhǔn)確顯示時(shí)間（顯示格式為時(shí)時(shí)：分分：秒秒，24小時(shí)制），可隨時(shí)進(jìn)行時(shí)間調(diào)整，具有鬧鐘時(shí)間設(shè)置、鬧鐘開/關(guān)、止鬧功能，能夠?qū)r(shí)鐘所在的環(huán)境溫度進(jìn)行測量并顯示。設(shè)計(jì)以硬件軟件化為指導(dǎo)思想，充分發(fā)揮單片機(jī)功能，大部分功能通過軟件編程來實(shí)現(xiàn)，電路簡單明了，系統(tǒng)穩(wěn)定性

41、高。同時(shí)，該時(shí)鐘系統(tǒng)還具有功耗小、成本低的特點(diǎn)，具有很強(qiáng)的實(shí)用性。由于系統(tǒng)所用元器件較少，單片機(jī)所被占用的I/O口不多，因此系統(tǒng)具有一定的可擴(kuò)展性。</p><p>　　時(shí)鐘設(shè)計(jì)無淪是用離散邏輯、可編程邏輯，還是用全定制硅器件實(shí)現(xiàn)的任何數(shù)字設(shè)計(jì)，為了成功地操作，可靠的時(shí)鐘是非常關(guān)鍵的。設(shè)計(jì)不良的時(shí)鐘在極限的溫度、電壓或制造工藝的偏差情況下將導(dǎo)致錯(cuò)誤的行為，并且調(diào)試?yán)щy、花銷很大。在設(shè)計(jì)FPGA/CPLD時(shí)通常采用

42、幾種時(shí)鐘類型。時(shí)鐘可分為如下四種類型：全局時(shí)鐘、門控時(shí)鐘、多級邏輯時(shí)鐘和波動(dòng)式時(shí)鐘。多時(shí)鐘系統(tǒng)能夠包括上述四種時(shí)鐘類型的任意組合。</p><p>　　無論采用何種方式，電路中真實(shí)的時(shí)鐘樹也無法達(dá)到假定的理想時(shí)鐘，因此我們必須依據(jù)理想時(shí)鐘，建立一個(gè)實(shí)際工作時(shí)鐘模型來分析電路，這樣才可以使得電路的實(shí)際工作效果和預(yù)期的一樣。在實(shí)際的時(shí)鐘模型中，我們要考慮時(shí)鐘樹傳播中的偏斜、跳變和絕對垂直的偏差以及其它一些不確定因素。

43、</p><p>　　對于寄存器而言，當(dāng)時(shí)鐘工作沿到來時(shí)它的數(shù)據(jù)端應(yīng)該已經(jīng)穩(wěn)定，這樣才能保證時(shí)鐘工作沿采樣到數(shù)據(jù)的正確性，這段數(shù)據(jù)的預(yù)備時(shí)間我們稱之為建立時(shí)間（setup time）。數(shù)據(jù)同樣應(yīng)該在時(shí)鐘工作沿過去后保持一段時(shí)間，這段時(shí)間稱為保持時(shí)間（hold time）。</p><p>　　全局時(shí)鐘對于一個(gè)設(shè)計(jì)項(xiàng)目來說，全局時(shí)鐘(或同步時(shí)鐘)是最簡單和最可預(yù)測的時(shí)鐘。在PLD/FPGA設(shè)

44、計(jì)中最好的時(shí)鐘方案是：由專用的全局時(shí)鐘輸入引腳驅(qū)動(dòng)的單個(gè)主時(shí)鐘去鐘控設(shè)計(jì)項(xiàng)目中的每一個(gè)觸發(fā)器。只要可能就應(yīng)盡量在設(shè)計(jì)項(xiàng)目中采用全局時(shí)鐘。PLD/FPGA都具有專門的全局時(shí)鐘引腳，它直接連到器件中的每一個(gè)寄存器。這種全局時(shí)鐘提供器件中最短的時(shí)鐘到輸出的延時(shí)。</p><p>　　門控時(shí)鐘在許多應(yīng)用中，整個(gè)設(shè)計(jì)項(xiàng)目都采用外部的全局時(shí)鐘是不可能或不實(shí)際的。PLD具有乘積項(xiàng)邏輯陣列時(shí)鐘（即時(shí)鐘是由邏輯產(chǎn)生的），允許任意函

45、數(shù)單獨(dú)地鐘控各個(gè)觸發(fā)器。然而，當(dāng)你用陣列時(shí)鐘時(shí)，應(yīng)仔細(xì)地分析時(shí)鐘函數(shù)，以避免毛刺。</p><p>　　通常用陣列時(shí)鐘構(gòu)成門控時(shí)鐘。門控時(shí)鐘常常同微處理器接口有關(guān)，用地址線去控制寫脈沖。然而，每當(dāng)用組合函數(shù)鐘控觸發(fā)器時(shí)，通常都存在著門控時(shí)鐘。如果符合下述條件，門控時(shí)鐘可以象全局時(shí)鐘一樣可靠地工作：</p><p>　　驅(qū)動(dòng)時(shí)鐘的邏輯必須只包含一個(gè)“與”門或一個(gè)“或”門。如果采用任何附加邏在

46、某些工作狀態(tài)下，會(huì)出現(xiàn)競爭產(chǎn)生的毛刺。</p><p>　　邏輯門的一個(gè)輸入作為實(shí)際的時(shí)鐘，而該邏輯門的所有其它輸入必須當(dāng)成地址或控制線，它們遵守相對于時(shí)鐘的建立和保持時(shí)間的約束。</p><p>　　多級邏輯時(shí)鐘當(dāng)產(chǎn)生門控時(shí)鐘的組合邏輯超過一級(即超過單個(gè)的“與”門或“或”門)時(shí)，證設(shè)計(jì)項(xiàng)目的可靠性變得很困難。即使樣機(jī)或仿真結(jié)果沒有顯示出靜態(tài)險(xiǎn)象，但實(shí)際上仍然可能存在著危險(xiǎn)。通常，我們不

47、應(yīng)該用多級組合邏輯去鐘控PLD設(shè)計(jì)中的觸發(fā)器。</p><p>　　行波時(shí)鐘另一種流行的時(shí)鐘電路是采用行波時(shí)鐘，即一個(gè)觸發(fā)器的輸出用作另一個(gè)觸發(fā)器的時(shí)鐘輸入。如果仔細(xì)地設(shè)計(jì)，行波時(shí)鐘可以象全局時(shí)鐘一樣地可靠工作。然而，行波時(shí)鐘使得與電路有關(guān)的定時(shí)計(jì)算變得很復(fù)雜。行波時(shí)鐘在行波鏈上各觸發(fā)器的時(shí)鐘之間產(chǎn)生較大的時(shí)間偏移，并且會(huì)超出最壞情況下的建立時(shí)間、保持時(shí)間和電路中時(shí)鐘到輸出的延時(shí)，使系統(tǒng)的實(shí)際速度下降。</

48、p><p>　　多時(shí)鐘系統(tǒng)許多系統(tǒng)要求在同一個(gè)PLD內(nèi)采用多時(shí)鐘。最常見的例子是兩個(gè)異步微處理器器之間的接口，或微處理器和異步通信通道的接口。由于兩個(gè)時(shí)鐘信號之間要求一定的建立和保持時(shí)間，所以，上述應(yīng)用引進(jìn)了附加的定時(shí)約束條件。它們也會(huì)要求將某些異步信號同步化。</p><p>　　在許多應(yīng)用中只將異步信號同步化還是不夠的，當(dāng)系統(tǒng)中有兩個(gè)或兩個(gè)以上非同源時(shí)鐘的時(shí)候，數(shù)據(jù)的建立和保持時(shí)間很難得到