基于FPGA的信道誤碼測試儀設(shè)計(jì)與實(shí)現(xiàn).pdf

1、北京交通大學(xué)碩士學(xué)位論文基于FPGA的信道誤碼測試儀設(shè)計(jì)與實(shí)現(xiàn)姓名：方琪申請(qǐng)學(xué)位級(jí)別：碩士專業(yè)：信號(hào)與信息處理指導(dǎo)教師：胡紹海201106ABSTRACTABSTRACTBitE仃or脅e(BER)isVeDr砌uable鋤dimport觚ttoeVal腳enlepe墑manceofC0mmuIlication觚missiondeVicesortheq眥lityofammsIIlissionsystemAndtlleBERtesteri

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