at89c52單片機(jī)簡(jiǎn)介外文翻譯

1、<p><b>　　中文6065字</b></p><p>　　畢 業(yè) 設(shè) 計(jì)（譯 文）</p><p>　　題 目： 基于單片機(jī)和TDA5767HN的收音機(jī)系統(tǒng)設(shè)計(jì)</p><p>　　院 （系）： 自動(dòng)化學(xué)院 </p><p>　　專(zhuān) 業(yè)：

2、 自動(dòng)化 </p><p>　　班 級(jí)： 自動(dòng)1002班 </p><p>　　學(xué)生姓名： </p><p>　　導(dǎo)師姓名： 職稱(chēng)： 教授 </p><

3、p>　　An overview of microcontroller</p><p>　　Description</p><p>　　The AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read on

4、ly memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pinout. The on-chip Flash allows the program

5、memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip</p><p>　　Function characteristic</p><p>

6、;　　The AT89C52 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip os

7、cillator and clock circuitry. In addition, the AT89C52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowin

8、g the RAM, timer/counters, serial port and interrupt system to </p><p>　　Pin Description</p><p>　　VCC：Supply voltage.</p><p>　　GND：Ground.</p><p><b>　　Port 0：<

9、/b></p><p>　　Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.

10、Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups.Port 0 also receives the code bytes during Flash pro

11、gramming,and outputs the code bytes during programverification. External pullups are requ</p><p><b>　　Port 1：</b></p><p>　　Port 1 is an 8-bit bi-directional I/O port with internal pu

12、llups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being p

13、ulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.</p><p><b>　　Port 2：</b></p>

14、<p>　　Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they are pulled high by the internal pullups and ca

15、n be used as inputs. As inputs,Port 2 pins that are externally being pulled low will source current, because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory an

16、d during accesses to external data memory that use 16-bit addresses. In</p><p><b>　　Port 3：</b></p><p>　　Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 o

17、utput buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will sou

18、rce current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89C52 as listed below:</p><p>　　Port 3 also receives some control signals for Flash programming

19、 and verification.</p><p>　　RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.</p><p>　　ALE/PROG Address Latch Enable output pulse fo

20、r latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscilla

21、tor frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.</p><p>　　If desired, ALE operation can be dis

22、abled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroll

23、er is in external execution mode.</p><p>　　PSEN Program Store Enable is the read strobe to external program memory.When the AT89C52 is executing code from external program memory, PSEN is activated twice ea

24、ch machine cycle, except that two PSEN activations are skipped during each access to external data memory.</p><p>　　EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to

25、 fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program

26、executions.This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require12-volt VPP.</p><p>　　XTAL1Input to the inverting oscillator amplifier and input

27、to the internal clock operating circuit.</p><p>　　XTAL2Output from the inverting oscillator amplifier.</p><p>　　Oscillator Characteristics</p><p>　　XTAL1 and XTAL2 are the input and

28、 output, respectively,of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1.Either a quartz crystal or ceramic resonator may be used. To drive the device from an externa

29、l clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is

30、through a divide-by-two fli</p><p>　　Figure 1. Oscillator Connections Figure 2. External Clock Drive Configuration</p><p><b>　　Idle Mode</b></p><p>　　In idle m

31、ode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode.

32、 The idle mode can be terminated by any enabled interrupt or by a hardware reset.It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution,from where it left off,

33、 up to two machine cycles before the internal reset</p><p>　　Power-down Mode</p><p>　　In the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last i

34、nstruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not ch

35、ange the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to </p><p>　　Program Memory Lock Bits&

36、lt;/p><p>　　On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below.</p><p>　　When lock bit 1 is prog

37、rammed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necess

38、ary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.</p><p>　　Structure and function of the MCS-51 series</p><p&g

39、t;　　Structure and function of the MCS-51 series one-chip computer MCS-51 is a name of a piece of one-chip computer series which Intel Company produces. This company introduced 8 top-grade one-chip computers of MCS-51 ser

40、ies in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line of one-chip computer the chips have,such as8052, 8031, 8751, 80C51BH, 80C31BH,etc., their basic compositi

41、on, basic performance and instruction system are all the same.80</p><p>　　An one-chip computer system is made up of several following parts: ( 1) One microprocessor of 8 (CPU). ( 2) At slice data memory RAM

42、(128B/256B),it use not depositting not can reading /data that write, such as result not middle of operation, final result and data wanted to show, etc. ( 3) Procedure memory ROM/EPROM (4KB/8KB ), is used to preserve the

43、procedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chip computers, such as 8031 , 8032, 80C ,etc.. ( 4) F</p><p>　　There are ROM (procedure memory , can only read )

44、and RAM in8052 slices (data memory, can is it can write ) two to read, they have each independent memory address space, dispose way to be the same with general memory of computer. Procedure8052 memory and 8751 slice proc

45、edure memory capacity 4KB, address begin from 0000H, used for preserving the procedure and form constant. Data8052- 8751 8031 of memory data memory 128B, address false 00FH, use for middle result to deposit operation, th

46、e data are</p><p>　　8052 one-chip computer have four 8 walk abreast I/O port, call P0, P1, P2 and P3. Each port is 8 accurate two-way mouths, accounts for 32 pins altogether. Every one I/O line can be used a

47、s introduction and exported independently. Each port includes a latch (namely special function register ), one exports the driver and a introduction buffer . Make data can latch when outputting, data can buffer when maki

48、ng introduction , but four function of passway these self-same. Expand among the system of me</p><p>　　Output grade , P3 of mouth , P1 of P1 , connect with inside have load resistance of drawing , every one

49、of they can drive 4 Model LS TTL load to output. As while inputting the mouth, any TTL or NMOS circuit can drive P1 of8052 one-chip computers as P3 mouth in a normal way . Because draw resistance on output grade of them

50、have, can open a way collector too or drain-source resistance is it urge to open a way, do not need to have the resistance of drawing outerly . Mouths are all accurate two-way </p><p>　　Restore to the throne

51、 the circuit and include two parts outside in the chip entirely. Outside that circuit produce to restore to the throne signal (RST ) hand over to Schmitt's trigger, restore to the throne circuit sample to output , Sc

52、hmitt of trigger constantly in each S5P2 , machine of cycle in having one more , then just got and restored to the throne and operated the necessary signal insidly. Restore to the throne resistance of circuit generally,

53、electric capacity parameter suitable for 6 </p><p>　　With the costant growing consumption of fossil energy, global energy crisis and environmental problems have become more and more acute. Among various gree

54、n renewable energy resources, solar energy has drawn the attention from the scientific circles of various countries due to its unique advantages such as bountless storage content, cleaness and safety, and easiness to obt

55、ain. In particular, the application of solar photovoltaic technology has become a universal focus. China has relatively scarce</p><p>　　The major content of this subject includes the development and applicat

56、ion of the solar photovoltaic system, the classification of the solar photovoltaic system, solar photovoltaic cells, the design of DC (direct current) control system, settings of maximum power point tracking, circuit des

57、ign and determination of the capacity of the inverter, and the settings of three-phase transformer and the AC (alternating current) distribution system.</p><p>　　solar photovoltaic power, photovoltaic cells,

58、 DC (direct current) control system, AC (alternating current) distribution system.</p><p>　　The8052 microcontroller is an industry standard architecture that has broad acceptance, wide-ranging applications a

59、nd development tools available. There are numerous commercial vendors that supply this controller or have it integrated into some type of system-on-a-chip structure. Both MRC and IAμE chose this device to demonstrate two

60、 distinctly different technologies for hardening. The MRC example of this is to use temporal latches that require specific timing to ensure that single event effects</p><p>　　The objective of this work is th

61、e technology evaluation of the CULPRiT process [3] from IAμE. The process has been baselined against two other processes, the standard8052 commercial device from Intel and a version using state-of-the-art processing from

62、 Dallas Semiconductor. By performing this side-by-side comparison, the cost benefit, performance, and reliability trade study can be done.</p><p>　　In the performance of the technology evaluation, this task

63、developed hardware and software for testing microcontrollers. A thorough process was done to optimize the test process to obtain as complete an evaluation as possible. This included taking advantage of the available hard

64、ware and writing software that exercised the microcontroller such that all substructures of the processor were evaluated. This process is also leading to a more complete understanding of how to test complex structures, s

65、u</p><p>　　IV. TEST DEVICES</p><p>　　Three devices were used in this test evaluation. The first is the NASA CULPRIT device, which is the primary device to be evaluated. The other two devices are

66、 two versions of a commercial8052, manufactured by Intel and Dallas Semiconductor, respectively.</p><p>　　The Intel devices are the ROM less, CMOS version of the classic 8052 MCS-51 microcontroller. They are

67、 rated for operation at +5V, over a temperature range of 0 to 70 °C and at a clock speeds of 3.5 MHz to 24 MHz. They are manufactured in Intel’s P629.0 CHMOS III-E process.</p><p>　　The Dallas Semicondu

68、ctor devices are similar in that they are ROMless 8052 microcontrollers, but they are enhanced in various ways. They are rated for operation from 4.25 to 5.5 Volts over 0 to 70 °C at clock speeds up to 25 MHz. They

69、have a second full serial port built in, seven additional interrupts, a watchdog timer, a power fail reset, dual data pointers and variable speed peripheral access. In addition, the core is redesigned so that the machine

70、 cycle is shortened for most instructions, re</p><p>　　The CULPRiT technology device is a version of the MSC-51 family compatible C8052 HDL core licensed from the Ultra Low Power (ULP) process foundry. The

71、 CULPRiT technology C8052 device is designed to operate at a supply voltage of 500 mV and includes an on-chip input/output signal level-shifting interface with conventional higher voltage parts. The CULPRiT C8052 device

72、requires two separate supply voltages; the 500 mV and the desired interface voltage. The CULPRiT C8052 is ROMless and is intende</p><p>　　V. TEST HARDWARE</p><p>　　The8052 Device Under Test (DUT

73、) was tested as a component of a functional computer. Aside from DUT itself, the other components</p><p>　　of the DUT computer were removed from the immediate area of the irradiation beam. A small card (one

74、per DUT package type) with a unique hard-wired identifier byte contained the DUT, its crystal, and bypass capacitors (and voltage level shifters for the CULPRiT DUTs). This "DUT Board" was connected to the &quo

75、t;Main Board" by a short 60-conductor ribbon cable. The Main Board had all other components required to complete the DUT Computer, including some which nominally are not necessary in some designs</p><p>

76、;　　The DUT Computer and the Test Control Computer were connected via a serial cable and communications were established between the two by the Controller (that runs custom designed serial interface software). This Contro

77、ller software allowed for commanding of the DUT, downloading DUT Code to the DUT, and real-time error collection from the DUT during and post irradiation. A 1 Hz signal source provided an external watchdog timing signal

78、 to the DUT, whose watchdog output was monitored via an oscillo</p><p>　　VI. TEST SOFTWARE </p><p>　　The8052 test software concept is straightforward. It was designed to be a modular series of s

79、mall test programs each exercising a specific part of the DUT. Since each test was stand alone, they were loaded independently of each other for execution on the DUT. This ensured that only the desired portion of the8052

80、 DUT was exercised during the test and helped pinpoint location of errors that occur during testing. All test programs resided on the controller PC until loaded via the serial interface t</p><p>　　All test p

81、rograms implemented:</p><p>　　? An external Universal Asynchronous Receive and Transmit device (UART) for transmission of error information and communication to controller computer.</p><p>　　? A

82、n external real-time clock for data error tag.</p><p>　　? A watchdog routine designed to provide visual verification of8052 health and restart test code if necessary.</p><p>　　? A "foul-up&

83、quot; routine to reset program counter if it wanders out of code space.</p><p>　　? An external telemetry data storage memory to provide backup of data in the event of an interruption in data transmission.<

84、;/p><p>　　The brief description of each of the software tests used is given below. It should be noted that for each test, the returned telemetry (including time tag) was sent to both the test controller and the

85、 telemetry memory, giving the highest reliability that all data is captured.</p><p>　　Interrupt – This test used 4 of 6 available interrupt vectors (Serial, External, Timer0 Overflow, and Timer1 Overflow) to

86、 trigger routines that sequentially modified a value in the accumulator which was periodically compared to a known value. Unexpected values were transmitted with register information. </p><p>　　Logic – This

87、test performed a series of logic and math computations and provided three types of error identifications: 1) addition/subtraction, 2) logic and 3) multiplication/division. All miscompares of computations and expected res

88、ults were transmitted with other relevant register information. </p><p>　　Memory – This test loaded internal data memory at locations D:0x20 through D:0xff (or D:0x20 through D:0x080 for the CULPRiT DUT), in

89、directly, with an 0x55 pattern. Compares were performed continuously and miscompares were corrected while error information and register values were transmitted. </p><p>　　Program Counter -The program counte

90、r was used to continuously fetch constants at various offsets in the code. Constants were compared with known values and miscompares were transmitted along with relevant register information. </p><p>　　Regis

91、ters – This test loaded each of four (0,1,2,3) banks of general-purpose registers with either 0xAA (for banks 0 and 2) or 0x55 (for banks 1 and 3). The pattern was alternated in order to test the Program Status Word (PSW

92、) special function register, which controls general-purpose register bank selection. General-purpose register banks were then compared with their expected values. All miscompares were corrected and error information was

93、transmitted.</p><p>　　Special Function Registers (SFR) – This test used learned static values of 12 out 21 available SFRs and then constantly compared the learned value with the current one. Miscompares were

94、 reloaded with learned value and error information was transmitted. Stack – This test performed arithmetic by pushing and popping operands on the stack. Unexpected results were attributed to errors on the stack or to

95、 the stack pointer itself and were transmitted with relevant register information.</p><p>　　VII. TEST METHODOLOGY </p><p>　　The DUT Computer booted by executing the instruction code located at a

96、ddress 0x0000. Initially, the device at this location was an EPROM previously loaded with "Boot/Serial Loader" code. This code initialized the DUT Computer and interface through a serial connection to the contr

97、olling computer, the "Test Controller". The DUT Computer downloaded Test Code and put it into Program Code RAM (located on the Main Board of the DUT Computer). It then activated a circuit which simultaneously p

98、erformed t</p><p>　　The Test Control Computer always retained the ability to force the reset/remap function, regardless of the DUT Computer's functionality. Thus, if the test ran without a Single Event F

99、unctional Interrupt (SEFI) either the DUT Computer itself or the Test Controller could have terminated the test and allowed the post-test functions to be executed. If a SEFI occurred, the Test Controller forced a reboot