外文翻譯--at89c52單片機(jī)的介紹

1、<p><b>　　附錄3：外文翻譯</b></p><p>　　AT89C52 monolithic integrated circuit introduction</p><p>　　AT89C52 is the low voltage which American ATMEL Corporation produces, the high perform

2、ance CMOS 8 monolithic integrated circuits, internal may repeatedly scratch read-only program memory (PEROM) and 256bytes random access data-carrier storage (RAM) including 8k bytes which writes, the component uses ATMEL

3、 Corporation the high density, the non-volatility memory technology production, is compatible with the standard MCS-51 command system and 8052 product pins, internal sets at general 8 central pr</p><p>　　Fun

4、ction characteristic outline: </p><p>　　Below AT89C52 provides the standard function: 8k byte Flash dodges the fast memory, 256 byte internal RAM,32 I/O mouth line, 3 16 fixed time/counters, 6 vector two lev

5、el of interrupt structures, A full-duplex serial passes unguardedly, internal oscillator and clock electric circuit.At the same time, AT89C52 may fall to the 0HZ static state logical operation, and supports the electrici

6、ty saving working pattern which two kind of softwares may elect.The idle way stops CPU the work, but permits RAM,</p><p>　　The pin function shows </p><p>　　Vcc: Supply voltage </p><p&

7、gt;　　GND: Grounding</p><p>　　P0 mouth: The P0 mouth is one group of 8 leaks leads the way extremely the bidirectional I/O mouth, also is the address/data bus multiplying mouth.As outlet with when, each pote

8、ntial energy absorption current way actuates 8 TTL logic gate, when writes “1” to port P0, may take the high impedance input end uses.</p><p>　　When visits exterior data-carrier storage or the program memory

9、, when this group of mouth line segment transforms the address (low 8) and the data bus multiplying, pulls the resistance in the visit activation interior. </p><p>　　When Flash programming, P0 mouth receive

10、instruction byte, but when program check, when output order byte, verification, outside the request joins pulls the resistance</p><p>　　P1 mouth: P1 is in a belt interior pulls the resistance 8 bidirectional

11、 I/O mouth, the P1 output buffer may actuate (absorption or output current) 4 TTL logic gate.Writes “1” to the port, pulls the resistance through internal on to pull the port to the high level, this time may make the inp

12、ut port.When makes the input port use, because in internal existence pulls the resistance, some pin is pulled lowly by exterior signal when can output electric current (IIL).</p><p>　　With at89C51 similarity

13、 is, P1.0 and P1.1 also may take separately fixed time/the counter 2 exterior countings inputs (P1.0/T2) and inputs (P1.1/T2EX), see also table 1. </p><p>　　Flash programming and program check period, P1 rec

14、eives the low 8 bit address.</p><p>　　Table 1 P1.0 and P1.1 second function</p><p>　　P2 mouth: P2 is one has in the interior to pull the resistance 8 bidirectional I/O mouth, the P2 output buffe

15、r may actuate (absorption or output current) 4 TTL logic gate.Writes “1” to port P2, pulls the resistance through internal on to pull the port to the high level, this time may make the input port, when makes the input po

16、rt use, because in internal existence pulls the resistance, some pin is pulled lowly by exterior signal when can output electric current (IIL).</p><p>　　When visits exterior program memory or 16 bit address

17、exterior data-carrier storage (e.g. carries out the MOVX@DPTR instruction), the P2 mouth sends out the high 8 bit address data.When visits 8 bit addresses exterior data-carrier storage (for example carries out the MOVX@R

18、I instruction), the P2 mouth outputs the P2 latch the content</p><p>　　When Flash programming or verification, P2 also receives the top digit address and some control signal.</p><p>　　P3 mouth:

19、The P3 mouth is a group has in the interior to pull the resistance 8 bidirectional I/O mouth.The P3 mouth output buffer may actuate (absorption or output current) 4 TTL logic gate.Reads in “1” when to the P3 mouth, they

20、the position resistance are pulled by the interior in Gao Bingke the achievement to input the port.This time, will be pulled by the outside the low P3 mouth to use to pull resistance output current (IIL). </p><

21、;p>　　The P3 mouth besides took the general I/O mouth line, a more important use is its second function, the following table shows: </p><p>　　In addition, the P3 mouth also receives some to use in Flash do

22、dging the fast memory programming and the program check control signal.</p><p>　　RST: Replacement input.When the oscillator works, the RST pin will appear above two machine cycles the high level to cause the

23、 monolithic replacement.</p><p>　　ALE/PROG: When visits exterior program memory or the data-carrier storage, ALE (address lock saves permission) to output the pulse to use in the lock saving the address the

24、low 8 bytes.In ordinary circumstances, ALE still by clock oscilation frequency 1/6 output fixed pulse signal, therefore it may the foreign output clock or uses in fixed time the goal.Must pay attention: When visits exter

25、ior data-carrier storage will jump over a ALE pulse.</p><p>　　To Flash memory programming period, this pin also uses in inputting programming pulse (PROG). </p><p>　　If has the necessity, may th

26、rough to in special function register (SFR) area 8EH the unit D0 position position, be possible to forbid the ALE operation.After this position position, only then MOVX and the MOVC instruction can activate ALE.In additi

27、on, this pin can pull weakly high, when the monolithic integrated circuit carries out exterior procedure, should establish the ALE prohibition position to be invalid</p><p>　　PSEN: The procedure storage perm

28、its the (PSEN) output is exterior program memory reads the gating signal, when AT89C52 takes the instruction by exterior program memory (or data), each machine cycle two PSEN is effective, namely outputs two pulses.When

29、visits exterior data-carrier storage, will jump over two RSEN signals. </p><p>　　EA/VPP: Exterior visit permission.Wants to cause CPU only to visit exterior program memory (address is 0000H-FFFFH), the EA en

30、d must maintain the low level (earth).Must pay attention: If adds mil LB1 to program, when replacement the interior can lock saves the EA end condition.</p><p>　　If the EA end (meets the Vcc end) for the hig

31、h level, CPU carries out in the internal procedure memory instruction.</p><p>　　When the Flash memory programs, this pin adds on 12V programming permission power source VPP, certainly this must be this compo

32、nent is uses 12V to program voltage VPP.</p><p>　　XTAL1: Oscillator inverting amplifier and internal clock generator input end.</p><p>　　XTAL2: Oscillator inverting amplifier out-port. Special f

33、unction register: </p><p>　　In at89C52 internal memory, the 80H-FFH altogether 128 units for special function register (SFE), SFR address basement reflection as shown in Table 2.</p><p>　　All ad

34、dresses all are defined by no means, only then a part is defined from the 80H-FFH altogether 128 bytes, but also has quite a part not to define.To the definition unit read-write will not have been Yuan Xiao, the read-out

35、 value will be indefinite, but will read in the data will also lose.</p><p>　　Should not “1” not read in the data the definition unit, then will possibly entrust with the new function in these units in the f

36、uture product, in this case, after replacement these unit value always “0”. </p><p>　　AT89C52 besides with AT89C51 all fixed time/counters 0 and fixed time/counter 1, but also increased a fixed time/counter

37、2.Fixed time/the counter 2 control status byte is located T2CON、T2MOD (to see Table 4), the register to (RCA02H, RCAP2L) is the timer 2/automatic loads the register again under 16 capture ways or 16 automatic heavy loadi

38、ng way capture.</p><p>　　Interrupt register: </p><p>　　AT89C52 has 6 interrupt sources, 2 interrupt priorities, the IE register controls each interrupt position, in the IP register 6 interrupt s

39、ource each may decide as 2 superior</p><p>　　data-carrier storages: </p><p>　　AT89C52 has 256 byte internal RAM,80H-FFH high 128 bytes and the special function register (SFR) address is overlap,

40、 also is high 128 byte RAM and the special function register address is same, but in physics they are separated.</p><p>　　When an instruction visits the 7FH above dummy home address unit, in the instruction

41、uses the addressing way is different, also is the addressing way decision is visits high 128 byte RAM to visit the special function register.If the instruction is the direct addressing way for the visit special function

42、register.</p><p>　　For example, following direct addressing instruction visit special function register 0A0H (i.e. P2 mouth) address unit.</p><p>　　MOV 0A0H,#data</p><p>　　The indir

43、ect addressing instruction visits high 128 byte RAM, for example, in following indirect addressing instruction, the R0 content is 0A0H, then the visit data byte address is 0A0H, but is not the P2 mouth (0A0H).</p>

44、<p>　　MOV the @R0,#data</p><p>　　storehouse operation also is the indirect addressing way, therefore, high 128 bit data RAM also may take the storehouse area use.</p><p>　　Timer 0 and time

45、r 1:</p><p>　　The AT89C52 timer 0 and the timer 1 working and AT89C51 are same.</p><p><b>　　Timer 2:</b></p><p>　　The timer 2 is 16 fixed time/counters.It already may wh

46、en timer use, also may take the external event counter use, its working chooses by the special function register T2CON C/T2 position.The timer 2 has three workings: The capture way, the automatic heavy loading (upward or

47、 downward counting) the way and the baudrate generator way, the working chooses by the T2CON control position, see also table 4. </p><p>　　Table 4 timer 2 workings</p><p>　　The timer 2 is compos

48、ed by two 8 register TH2 and TL2, in the timer working, each machine cycle TL2 register value adds 1, because a machine cycle vibrates the clock constitution by 12, therefore, counting speed for oscilation frequency 1/12

49、.</p><p>　　When counting working, when on the T2 pin exterior input signal produces by 1 to 0 drops along, the register value adds 1, under this working, each machine cycle 5SP2 period, carries on the sampli

50、ng to exterior input. If picks in the first machine cycle the value is 1, but the value which picks in the next machine cycle is 0, then is following close on the next cyclical S3P1 period register adds 1.Because disting

51、uishes 1 to need 2 machine cycles to 0 jumps (24 durations of oscillation), therefor</p><p>　　Capture way:</p><p>　　Under the capture way, chooses two ways through T2CON control position EXEN2.I

52、f EXEN2=0, the timer 2 is 16 timers or the counter, when counting overflow, to the T2CON overflow symbolized TF2 sets at the position, simultaneously activates the interrupt.If looks up EXEN2=1, the timer 2 completes the

53、 same operation, But when the T2EX pin exterior input signal has 1 to 0 negative jumps, also appears in TH2 and the TL2 value is caught separately to in RCAP2H and RCAP2L.Moreover, the T2EX pin signal j</p><p&

54、gt;　　Automatic heavy loading (upward or downward counter) way: </p><p>　　When timer 2 work in 16 automatic heavy loading ways, can to its programming for upward or the downward counting way, this function ma

55、y (see Table 5) through special function register T2CON the DCEN position (permission downward counting) choose.When replacement, the DCEN position “0”, the timer 2 defaults establishes as the upward counting. When DCEN

56、sets at the position, the timer 2 already may count upwardly also may the downward counting, this is decided by the T2EX pin value, see also Figur</p><p>　　When DCEN sets at the position, the timer 2 already

57、 may count upwardly also may the downward counting, this is decided by the T2EX pin value, see also Figure 5, when DCEN=0, the timer 2 automatic setups for the upward counting, under this way, in the T2CON EXEN2 control

58、position have two kind of choices, if EXEN2=0, the timer 2 for the upward counting to the 0FFFFH overflow, sets at the position TF2 activation interrupt, simultaneously 16 counter register RCAP2H and the RCAP2L heavy loa

59、ding, RCA</p><p>　　Baudrate generator: </p><p>　　When T2CON (Table 3) TCLK and RCLK set at the position, fixed time/the counter 2 takes the baudrate generator use.If fixed time/the counter 2 too

60、k the transmitter or the receiver, its transmission and the receive baudrate may be different, the timer 1 uses in other functions, as shown in Figure 7.If RCLK and TCLK set at the position, then timer 2 work in baudrate

61、 generator way.</p><p>　　The baudrate generator way and the automatic heavy loading way are similar, under this way, the TH2 turn over causes the timer 2 registers is important the new loading with in RCAP2H

62、 and the RCAP2L 16 figures, this value establishes by the software.</p><p>　　In the way 1 and the way in 3, the baudrate determined by the timer 2 overflow speeds according to the equation below that,Way 1 a

63、nd 3 baudrate = timer overflow rate /16</p><p>　　The timer already can work in fixed time the way also can work in the counting way, in the majority applications, is the work in fixed time the way (C/T2=0).T

64、he timer 2 took when baudrate generator, with as the timer operation is different, when usual achievement timer, (1/12 oscilation frequency) checks the value in each machine cycle to add 1, but took when baudrate generat

65、or use, (1/2 oscilation frequency) the register value adds 1 in each condition time. The baudrate formula is as follows:</p><p>　　The way 1 and 3 baudrate = oscilation frequency/{32×[65536-(RCAP2H, RCAP

66、2L)]}</p><p>　　in the formula (RCAP2H, RCAP2L) is in RCAP2H and RCAP2L 16 does not have the sign digit.</p><p>　　The timer 2 took the baudrate generator use electric circuit as shown in Figure 7

67、.In when T2CON RCLK or TCLK=1, the baudrate working only then is effective. In the baudrate generator working, the TH2 turn over cannot cause TF2 to set at the position, therefore does not have the interrupt.But if EXEN2

68、 sets at the position, also the T2EX end produces by 1 to 0 negative jumps, then can cause EXF2 to set at the position, this time cannot load (RCAP2H, RCAP2L) content in TH2 and TL2.Therefore, when t</p><p>

69、　　But however, may read to RCAP2 cannot write, because the write operation will be the reload, the write operation possibly command writes with/or the heavy loading makes a mistake.In visits timer 2 or in front of the RC

70、AP2 register, should (eliminate the timer closure TR2).</p><p>　　The programmable clock outputs: </p><p>　　The timer 2 may output a dutyfactor through the programming from P1.0 is 50% clock sign

71、al, as shown in Figure 8.The P1.0 pin besides is a standard I/O mouth, but also may cause it through the programming to take fixed time/the counter 2 exterior clock inputs and the output dutyfactor 50% clock pulse.When t

72、he clock oscilation frequency is 16MHz, outputs the clock frequency range is 61Hz-4MHz.</p><p>　　When establishes fixed time/the counter 2 as the clock generator, C/T2(T2CON.1)=0, T2OE(T2MOD.1)=1, must or st

73、ops the timer by TR2(T2CON.2) start.The clock output frequency is decided in the oscilation frequency and the timer 2 catches the register (RCAP2H, RCAP2L) reload value, the formula is as follows:</p><p>　　T

74、he output clock frequency = oscillator frequency/{4×[65536-(RCAP2H, RCAP2L)]}</p><p>　　under the clock output way, the timer 2 turn over cannot have the interrupt, this characteristic with took when bau

75、drate generator use is similar.When the timer 2 takes the baudrate generator use, Also may take the clock generator use, but needs to pay attention is the baudrate and the clock output frequency cannot separate the deter

76、mination, this is because they with use RCAP2H and RCAP2L.</p><p>　　AT89C52單片機(jī)的介紹</p><p>　　AT89C52是美國(guó)ATMEL公司生產(chǎn)的低電壓，高性能CMOS 8位單片機(jī)，片內(nèi)含8k bytes的可反復(fù)擦寫(xiě)的只讀程序存儲(chǔ)器（PEROM）和256bytes的隨機(jī)存取數(shù)據(jù)存儲(chǔ)器（RAM

77、），器件采用ATMEL公司的高密度、非易失性存儲(chǔ)技術(shù)生產(chǎn)，與標(biāo)準(zhǔn)MCS－51指令系統(tǒng)及8052產(chǎn)品引腳兼容，片內(nèi)置通用8位中央處理器（CPU）和Flash存儲(chǔ)單元，功能強(qiáng)大AT89C52單片機(jī)適合于許多較為復(fù)雜控制應(yīng)用場(chǎng)合。</p><p><b>　　功能特性概述：</b></p><p>　　AT89C52提供以下標(biāo)準(zhǔn)功能：8k字節(jié)Flash閃速存儲(chǔ)器，256字節(jié)

78、內(nèi)部RAM，32個(gè)I/O口線，3個(gè)16位定時(shí)/計(jì)數(shù)器，一個(gè)6向量?jī)杉?jí)中斷結(jié)構(gòu)，一個(gè)全雙工串行通信口，片內(nèi)振蕩器及時(shí)鐘電路。同時(shí)，AT89C52可降至0HZ的靜態(tài)邏輯操作，并支持兩種軟件可選的節(jié)電工作模式。空閑方式停止CPU的工作，但允許RAM，定時(shí)/計(jì)數(shù)器，串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方式保存RAM中的內(nèi)容，但振蕩器停止工作并禁止其它所有部件工作直到下一個(gè)硬件復(fù)位。</p><p><b>　　引

79、腳功能說(shuō)明 </b></p><p><b>　　Vcc：電源電壓 </b></p><p><b>　　GND：地線 </b></p><p>　　P0口：P0口是一組8位漏極開(kāi)路型雙向I/O口，也即地址/數(shù)據(jù)總線復(fù)用口。作為輸出口用時(shí)，每位能吸收電流的方式驅(qū)動(dòng)8個(gè)TTL邏輯門(mén)電路，對(duì)端口P0寫(xiě)“1”時(shí)，可作

80、為高阻抗輸入端用。 </p><p>　　在訪問(wèn)外部數(shù)據(jù)存儲(chǔ)器或程序存儲(chǔ)器時(shí)，這組口線分時(shí)轉(zhuǎn)換地址（低8位）和數(shù)據(jù)總線復(fù)用，在訪問(wèn)期間激活內(nèi)部上拉電阻。 </p><p>　　在Flash編程時(shí)，P0口接收指令字節(jié)，而在程序校驗(yàn)時(shí)，輸出指令字節(jié)，校驗(yàn)時(shí)，要求外接上拉電阻</p><p>　　P1口：P1是一個(gè)帶內(nèi)部上拉電阻的8位雙向I/O口，P1的輸出緩沖級(jí)可驅(qū)動(dòng)（

81、吸收或輸出電流）4個(gè)TTL邏輯門(mén)電路。對(duì)端口寫(xiě)“1”，通過(guò)內(nèi)部的上拉電阻把端口拉到高電平，此時(shí)可作輸入口。作輸入口使用時(shí)，因?yàn)閮?nèi)部存在上拉電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流（IIL）。</p><p>　　與AT89C51不同之處是，P1.0和P1.1還可分別作為定時(shí)/計(jì)數(shù)器2的外部計(jì)數(shù)輸入（P1.0/T2）和輸入（P1.1/T2EX），參見(jiàn)表1。 </p><p>　　Flas

82、h編程和程序校驗(yàn)期間，P1接收低8位地址。</p><p>　　表1　P1.0和P1.1的第二功能</p><p>　　P2口：P2是一個(gè)帶有內(nèi)部上拉電阻的8位雙向I/O口，P2的輸出緩沖級(jí)可驅(qū)動(dòng)（吸收或輸出電流）4個(gè)TTL邏輯門(mén)電路。對(duì)端口P2寫(xiě)“1”，通過(guò)內(nèi)部的上拉電阻把端口拉到高電平，此時(shí)可作輸入口，作輸入口使用時(shí)，因?yàn)閮?nèi)部存在上拉電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流（IIL

83、）。</p><p>　　在訪問(wèn)外部程序存儲(chǔ)器或16位地址的外部數(shù)據(jù)存儲(chǔ)器（例如執(zhí)行MOVX＠DPTR指令）時(shí)，P2口送出高8位地址數(shù)據(jù)。在訪問(wèn)8位地址的外部數(shù)據(jù)存儲(chǔ)器（如執(zhí)行MOVX＠RI指令）時(shí)，P2口輸出P2鎖存器的內(nèi)容</p><p>　　Flash編程或校驗(yàn)時(shí)，P2亦接收高位地址和一些控制信號(hào)。</p><p>　　P3口：P3口是一組帶有內(nèi)部上拉電阻的8

84、位雙向I/O口。P3口輸出緩沖級(jí)可驅(qū)動(dòng)（吸收或輸出電流）4個(gè)TTL邏輯門(mén)電路。對(duì)P3口寫(xiě)入“1”時(shí)，它們被內(nèi)部上位電阻拉高并可作為輸入端口。此時(shí)，被外部拉低的P3口將用上拉電阻輸出電流（IIL）。</p><p>　　P3口除了作為一般的I/O口線外，更重要的用途是它的第二功能，如下表所示： </p><p>　　此外，P3口還接收一些用于Flash閃速存儲(chǔ)器編程和程序校驗(yàn)的控制信號(hào)。&l

85、t;/p><p>　　RST：復(fù)位輸入。當(dāng)振蕩器工作時(shí)，RST引腳出現(xiàn)兩個(gè)機(jī)器周期以上高電平將使單片復(fù)位。</p><p>　　ALE/PROG：當(dāng)訪問(wèn)外部程序存儲(chǔ)器或數(shù)據(jù)存儲(chǔ)器時(shí)，ALE（地址鎖存允許）輸出脈沖用于鎖存地址的低8位字節(jié)。一般情況下，ALE仍以時(shí)鐘振蕩頻率的1/6輸出固定的脈沖信號(hào)，因此它可對(duì)外輸出時(shí)鐘或用于定時(shí)目的。要注意的是：每當(dāng)訪問(wèn)外部數(shù)據(jù)存儲(chǔ)器時(shí)將跳過(guò)一個(gè)ALE脈沖。

86、</p><p>　　對(duì)Flash存儲(chǔ)器編程期間，該引腳還用于輸入編程脈沖（PROG）。 </p><p>　　如有必要，可通過(guò)對(duì)特殊功能寄存器（SFR）區(qū)中的8EH單元的D0位置位，可禁止ALE操作。該位置位后，只有一條MOVX和MOVC指令才能將ALE激活。此外，該引腳會(huì)被微弱拉高，單片機(jī)執(zhí)行外部程序時(shí)，應(yīng)設(shè)置ALE禁止位無(wú)效</p><p>　　PSEN：程序

87、儲(chǔ)存允許（PSEN）輸出是外部程序存儲(chǔ)器的讀選通信號(hào)，當(dāng)AT89C52由外部程序存儲(chǔ)器取指令（或數(shù)據(jù)）時(shí)，每個(gè)機(jī)器周期兩次PSEN有效，即輸出兩個(gè)脈沖。在此期間，當(dāng)訪問(wèn)外部數(shù)據(jù)存儲(chǔ)器，將跳過(guò)兩次RSEN信號(hào)。 </p><p>　　EA/VPP：外部訪問(wèn)允許。欲使CPU僅訪問(wèn)外部程序存儲(chǔ)器（地址為0000H－FFFFH），EA端必須保持低電平（接地）。需注意的是：如果加密位LB1被編程，復(fù)位時(shí)內(nèi)部會(huì)鎖存EA端狀態(tài)

88、。</p><p>　　如EA端為高電平（接Vcc端），CPU則執(zhí)行內(nèi)部程序存儲(chǔ)器中的指令。</p><p>　　Flash存儲(chǔ)器編程時(shí)，該引腳加上+12V的編程允許電源VPP，當(dāng)然這必須是該器件是使用12V編程電壓VPP。</p><p>　　XTAL1：振蕩器反相放大器的及內(nèi)部時(shí)鐘發(fā)生器的輸入端。</p><p>　　XTAL2：振蕩器反

89、相放大器的輸出端。</p><p><b>　　特殊功能寄存器：</b></p><p>　　AT89C52片內(nèi)存儲(chǔ)器中，80H－FFH共128個(gè)單元為特殊功能寄存器（SFE），SFR的地址窨映象如表2所示。</p><p>　　并非所有的地址都被定義，從80H－FFH共128個(gè)字節(jié)只有一部分被定義，還有相當(dāng)一部分沒(méi)有定義。對(duì)沒(méi)有定義的單元讀寫(xiě)

90、將是元效的，讀出的數(shù)值將不確定，而寫(xiě)入的數(shù)據(jù)也將丟失。</p><p>　　不應(yīng)將數(shù)據(jù)“1”寫(xiě)入未定義的單元，則于這些單元在將來(lái)的產(chǎn)品中可能賦予新的功能，在這種情況下，復(fù)位后這些單元數(shù)值總是“0”。</p><p>　　AT89C52除了與AT89C51所有的定時(shí)/計(jì)數(shù)器0和定時(shí)/計(jì)數(shù)器1外，還增加了一個(gè)定時(shí)/計(jì)數(shù)器2。定時(shí)/計(jì)數(shù)器2的控制狀態(tài)位位于T2CON、T2MOD（見(jiàn)表4），寄存器

91、對(duì)（RCA02H、RCAP2L）是定時(shí)器2在16位捕獲方式或16位自動(dòng)重裝載方式下的捕獲/自動(dòng)重裝載寄存器。</p><p><b>　　中斷寄存器：</b></p><p>　　AT89C52有6個(gè)中斷源，2個(gè)中斷優(yōu)先級(jí)，IE寄存器控制各中斷位，IP寄存器中6個(gè)中斷源的每一個(gè)可定為2個(gè)優(yōu)</p><p><b>　　數(shù)據(jù)存儲(chǔ)器：&l

92、t;/b></p><p>　　AT89C52有256個(gè)字節(jié)的內(nèi)部RAM，80H－FFH高128個(gè)字節(jié)與特殊功能寄存器（SFR）地址是重疊的，也就是高128字節(jié)的RAM和特殊功能寄存器的地址是相同的，但物理上它們是分開(kāi)的。</p><p>　　當(dāng)一條指令訪問(wèn)7FH以上的內(nèi)部地址單元時(shí)，指令中使用的尋址方式是不同的，也即尋址方式?jīng)Q定是訪問(wèn)高128字節(jié)RAM還是訪問(wèn)特殊功能寄存器。如果指

93、令是直接尋址方式則為訪問(wèn)特殊功能寄存器。</p><p>　　例如，下面的直接尋址指令訪問(wèn)特殊功能寄存器0A0H（即P2口）地址單元。</p><p>　　MOV　0A0H，＃data</p><p>　　間接尋址指令訪問(wèn)高128字節(jié)RAM，例如，下面的間接尋址指令中，R0的內(nèi)容為0A0H，則訪問(wèn)數(shù)據(jù)字節(jié)地址為0A0H，而不是P2口（0A0H）。</p>

94、<p>　　MOV?。繰0，＃data</p><p>　　堆棧操作也是間接尋址方式，所以，高128位數(shù)據(jù)RAM亦可作為堆棧區(qū)使用。</p><p>　　定時(shí)器0和定時(shí)器1：</p><p>　　AT89C52的定時(shí)器0和定時(shí)器1的工作方式與AT89C51相同。</p><p><b>　　定時(shí)器2：</b>

95、;</p><p>　　定時(shí)器2是一個(gè)16位定時(shí)/計(jì)數(shù)器。它既可當(dāng)定時(shí)器使用，也可作為外部事件計(jì)數(shù)器使用，其工作方式由特殊功能寄存器T2CON的C/T2位選擇。定時(shí)器2有三種工作方式：捕獲方式，自動(dòng)重裝載（向上或向下計(jì)數(shù)）方式和波特率發(fā)生器方式，工作方式由T2CON的控制位來(lái)選擇，參見(jiàn)表4。</p><p>　　表4　定時(shí)器2工作方式</p><p>　　定時(shí)器2由

96、兩個(gè)8位寄存器TH2和TL2組成，在定時(shí)器工作方式中，每個(gè)機(jī)器周期TL2寄存器的值加1，由于一個(gè)機(jī)器周期由12個(gè)振蕩時(shí)鐘構(gòu)成，因此，計(jì)數(shù)速率為振蕩頻率的1/12。</p><p>　　在計(jì)數(shù)工作方式時(shí)，當(dāng)T2引腳上外部輸入信號(hào)產(chǎn)生由1至0的下降沿時(shí)，寄存器的值加1，在這種工作方式下，每個(gè)機(jī)器周期的5SP2期間，對(duì)外部輸入進(jìn)行采樣。若在第一個(gè)機(jī)器周期中采到的值為1，而在下一個(gè)機(jī)器周期中采到的值為0，則在緊跟著的下一

97、個(gè)周期的S3P1期間寄存器加1。由于識(shí)別1至0的跳變需要2個(gè)機(jī)器周期（24個(gè)振蕩周期），因此，最高計(jì)數(shù)速率為振蕩頻率的1/24。為確保采樣的正確性，要求輸入的電平在變化前至少保持一個(gè)完整周期的時(shí)間，以保證輸入信號(hào)至少被采樣一次。</p><p><b>　　捕獲方式：</b></p><p>　　在捕獲方式下，通過(guò)T2CON控制位EXEN2來(lái)選擇兩種方式。如果EXEN

98、2＝0，定時(shí)器2是一個(gè)16位定時(shí)器或計(jì)數(shù)器，計(jì)數(shù)溢出時(shí)，對(duì)T2CON的溢出標(biāo)志TF2置位，同時(shí)激活中斷。如查EXEN2＝1，定時(shí)器2完成相同的操作，而當(dāng)T2EX引腳外部輸入信號(hào)發(fā)生1至0負(fù)跳變時(shí)，也出現(xiàn)TH2和TL2中的值分別被捕獲到RCAP2H和RCAP2L中。另外，T2EX引腳信號(hào)的跳變使得T2CON中的EXF2置位，與TF2相仿，EXF2也會(huì)活中斷。捕獲方式如圖4所示。</p><p>　　自動(dòng)重裝載（向上

99、或向下計(jì)數(shù)器）方式：</p><p>　　當(dāng)定時(shí)器2工作于16位自動(dòng)重裝載方式時(shí)，能對(duì)其編程為向上或向下計(jì)數(shù)方式，這個(gè)功能可通過(guò)特殊功能寄存器T2CON（見(jiàn)表5）的DCEN位（允許向下計(jì)數(shù)）來(lái)選擇的。復(fù)位時(shí)，DCEN位置“0”，定時(shí)器2默認(rèn)設(shè)置為向上計(jì)數(shù)。當(dāng)DCEN置位時(shí)，定時(shí)器2既可向上計(jì)數(shù)也可向下計(jì)數(shù)，這取決于T2EX引腳的值，參見(jiàn)圖5，當(dāng)DCEN＝0時(shí)，定時(shí)器2自動(dòng)設(shè)置為向上計(jì)數(shù)，在這種方式下，T2CON中

100、的EXEN2控制位有兩種選擇，若EXEN2＝0，定時(shí)器2為向上計(jì)數(shù)至0FFFFH溢出，置位TF2激活中斷，同時(shí)把16位計(jì)數(shù)寄存器RCAP2H和RCAP2L重裝載，RCAP2H和RCAP2L的值可由軟件預(yù)置。若EXEN2＝1，定時(shí)器2的16位重裝載由溢出或外部輸入端T2EX從1至0的下降沿觸發(fā)。這個(gè)脈沖使EXF2置位，如果中斷允許，同樣產(chǎn)生中斷。</p><p>　　當(dāng)DCEN＝1時(shí)，允許定時(shí)器2向上或向下計(jì)數(shù)，如