at89c51單片機(jī)外文翻譯

1、<p>　　AT89C51的介紹</p><p>　?。ㄔ某鎏帲篽ttp：//yang63.go.nease.net/resource/mcu.htm）</p><p><b>　　描述</b></p><p>　　AT89C51是一個(gè)低電壓，高性能CMOS8位單片機(jī)帶有4K字節(jié)的可反復(fù)擦寫(xiě)的程序存儲(chǔ)器（PENROM）。和128字節(jié)

2、的存取數(shù)據(jù)存儲(chǔ)器（RAM），這種器件采用ATMEL公司的高密度、不容易丟失存儲(chǔ)技術(shù)生產(chǎn)，并且能夠與MCS-51系列的單片機(jī)兼容。片內(nèi)含有8位中央處理器和閃爍存儲(chǔ)單元，有較強(qiáng)的功能的AT89C51單片機(jī)能夠被應(yīng)用到控制領(lǐng)域中。</p><p><b>　　功能特性</b></p><p>　　AT89C51提供以下的功能標(biāo)準(zhǔn)：4K字節(jié)閃爍存儲(chǔ)器，128字節(jié)隨機(jī)存取數(shù)據(jù)存

3、儲(chǔ)器，32個(gè)I/O口，2個(gè)16位定時(shí)/計(jì)數(shù)器，1個(gè)5向量?jī)杉?jí)中斷結(jié)構(gòu)，1個(gè)串行通信口，片內(nèi)震蕩器和時(shí)鐘電路。另外，AT89C51還可以進(jìn)行0HZ的靜態(tài)邏輯操作，并支持兩種軟件的節(jié)電模式。閑散方式停止中央處理器的工作，能夠允許隨機(jī)存取數(shù)據(jù)存儲(chǔ)器、定時(shí)/計(jì)數(shù)器、串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方式保存隨機(jī)存取數(shù)據(jù)存儲(chǔ)器中的內(nèi)容，但震蕩器停止工作并禁止其它所有部件的工作直到下一個(gè)復(fù)位。</p><p><b&g

4、t;　　引腳描述</b></p><p>　　VCC：電源電壓 </p><p><b>　　GND：地</b></p><p><b>　　P0口：</b></p><p>　　P0口是一組8位漏極開(kāi)路雙向I/O口，即地址/數(shù)據(jù)總線復(fù)用口。作為輸出口時(shí)，每一個(gè)管腳都能夠驅(qū)動(dòng)8個(gè)T

5、TL電路。當(dāng)“1”被寫(xiě)入P0口時(shí)，每個(gè)管腳都能夠作為高阻抗輸入端。P0口還能夠在訪問(wèn)外部數(shù)據(jù)存儲(chǔ)器或程序存儲(chǔ)器時(shí)，轉(zhuǎn)換地址和數(shù)據(jù)總線復(fù)用，并在這時(shí)激活內(nèi)部的上拉電阻。P0口在閃爍編程時(shí)，P0口接收指令，在程序校驗(yàn)時(shí)，輸出指令，需要接電阻。</p><p><b>　　P1口：</b></p><p>　　P1口一個(gè)帶內(nèi)部上拉電阻的8位雙向I/O口，P1的輸出緩沖級(jí)可驅(qū)

6、動(dòng)4個(gè)TTL電路。對(duì)端口寫(xiě)“1”，通過(guò)內(nèi)部的電阻把端口拉到高電平，此時(shí)可作為輸入口。因?yàn)閮?nèi)部有電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)輸出一個(gè)電流。閃爍編程時(shí)和程序校驗(yàn)時(shí)，P1口接收低8位地址。</p><p><b>　　P2口：</b></p><p>　　P2口是一個(gè)內(nèi)部帶有上拉電阻的8位雙向I/O口，P2的輸出緩沖級(jí)可驅(qū)動(dòng)4個(gè)TTL電路。對(duì)端口寫(xiě)“1”，通過(guò)內(nèi)部的電阻把

7、端口拉到高電平，此時(shí)，可作為輸入口。因?yàn)閮?nèi)部有電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流。在訪問(wèn)外部程序存儲(chǔ)器或16位地址的外部數(shù)據(jù)存儲(chǔ)器時(shí)，P2口送出高8位地址數(shù)據(jù)。在訪問(wèn)8位地址的外部數(shù)據(jù)存儲(chǔ)器時(shí)，P2口線上的內(nèi)容在整個(gè)運(yùn)行期間不變。閃爍編程或校驗(yàn)時(shí)，P2口接收高位地址和其它控制信號(hào)。</p><p><b>　　P3口：</b></p><p>　　P3口是一

8、組帶有內(nèi)部電阻的8位雙向I/O口，P3口輸出緩沖故可驅(qū)動(dòng)4個(gè)TTL電路。對(duì)P3口寫(xiě)如“1”時(shí)，它們被內(nèi)部電阻拉到高電平并可作為輸入端時(shí)，被外部拉低的P3口將用電阻輸出電流。</p><p>　　P3口除了作為一般的I/O口外，更重要的用途是它的第二功能，如下表所示：</p><p>　　P3口還接收一些用于閃爍存儲(chǔ)器編程和程序校驗(yàn)的控制信號(hào)。</p><p><

9、;b>　　RST：</b></p><p>　　復(fù)位輸入。當(dāng)震蕩器工作時(shí)，RET引腳出現(xiàn)兩個(gè)機(jī)器周期以上的高電平將使單片機(jī)復(fù)位。</p><p><b>　　ALE/：</b></p><p>　　當(dāng)訪問(wèn)外部程序存儲(chǔ)器或數(shù)據(jù)存儲(chǔ)器時(shí)，ALE輸出脈沖用于鎖存地址的低8位字節(jié)。即使不訪問(wèn)外部存儲(chǔ)器，ALE以時(shí)鐘震蕩頻率的1/16輸

10、出固定的正脈沖信號(hào)，因此它可對(duì)輸出時(shí)鐘或用于定時(shí)目的。要注意的是：每當(dāng)訪問(wèn)外部數(shù)據(jù)存儲(chǔ)器時(shí)將跳過(guò)一個(gè)ALE脈沖時(shí)，閃爍存儲(chǔ)器編程時(shí)，這個(gè)引腳還用于輸入編程脈沖。如果必要，可對(duì)特殊寄存器區(qū)中的8EH單元的D0位置禁止ALE操作。這個(gè)位置后只有一條MOVX和MOVC指令A(yù)LE才會(huì)被應(yīng)用。此外，這個(gè)引腳會(huì)微弱拉高，單片機(jī)執(zhí)行外部程序時(shí)，應(yīng)設(shè)置ALE無(wú)效。</p><p><b>　　PSEN：</b&g

11、t;</p><p>　　程序儲(chǔ)存允許輸出是外部程序存儲(chǔ)器的讀選通信號(hào)，當(dāng)AT89C51由外部程序存儲(chǔ)器讀取指令時(shí)，每個(gè)機(jī)器周期兩次PSEN 有效，即輸出兩個(gè)脈沖。在此期間，當(dāng)訪問(wèn)外部數(shù)據(jù)存儲(chǔ)器時(shí)，這兩次有效的PSEN 信號(hào)不出現(xiàn)。</p><p><b>　　EA/VPP：</b></p><p>　　外部訪問(wèn)允許。欲使中央處理器僅訪問(wèn)外部程

12、序存儲(chǔ)器，EA端必須保持低電平。需要注意的是：如果加密位LBI被編程，復(fù)位時(shí)內(nèi)部會(huì)鎖存EA端狀態(tài)。如EA端為高電平，CPU則執(zhí)行內(nèi)部程序存儲(chǔ)器中的指令。閃爍存儲(chǔ)器編程時(shí)，該引腳加上+12V的編程允許電壓VPP，當(dāng)然這必須是該器件是使用12V編程電壓VPP。</p><p>　　XTAL1：震蕩器反相放大器及內(nèi)部時(shí)鐘發(fā)生器的輸入端。</p><p>　　XTAL2：震蕩器反相放大器的輸出端。

13、</p><p><b>　　時(shí)鐘震蕩器</b></p><p>　　AT89C51中有一個(gè)用于構(gòu)成內(nèi)部震蕩器的高增益反相放大器，引腳XTAL1和XTAL2分別是該放大器的輸入端和輸出端。這個(gè)放大器與作為反饋元件的片外石英晶體或陶瓷諧振器一起構(gòu)成自然震蕩器。 外接石英晶體及電容C1，C2接在放大器的反饋回路中構(gòu)成并聯(lián)震蕩電路。對(duì)外接電容C1，C2雖然沒(méi)有十分嚴(yán)格的要求

14、，但電容容量的大小會(huì)輕微影響震蕩頻率的高低、震蕩器工作的穩(wěn)定性、起振的難易程序及溫度穩(wěn)定性。如果使用石英晶體，我們推薦電容使用30PF±10PF，而如果使用陶瓷振蕩器建議選擇40PF±10PF。用戶也可以采用外部時(shí)鐘。采用外部時(shí)鐘的電路如圖示。這種情況下，外部時(shí)鐘脈沖接到XTAL1端，即內(nèi)部時(shí)鐘發(fā)生器的輸入端，XTAL2則懸空。由于外部時(shí)鐘信號(hào)是通過(guò)一個(gè)2分頻觸發(fā)器后作為內(nèi)部時(shí)鐘信號(hào)的，所以對(duì)外部時(shí)鐘信號(hào)的占空比沒(méi)有

15、特殊要求，但最小高電平持續(xù)時(shí)間和最大的低電平持續(xù)時(shí)間應(yīng)符合產(chǎn)品技術(shù)條件的要求。</p><p>　　內(nèi)部振蕩電路 外部振蕩電路</p><p><b>　　閑散節(jié)電模式</b></p><p>　　AT89C51有兩種可用軟件編程的省電模式，它們是閑散模式和掉電工作模式。這兩種方

16、式是控制專用寄存器PCON中的PD和IDL位來(lái)實(shí)現(xiàn)的。PD是掉電模式，當(dāng)PD=1時(shí)，激活掉電工作模式，單片機(jī)進(jìn)入掉電工作狀態(tài)。IDL是閑散等待方式，當(dāng)IDL=1，激活閑散工作狀態(tài)，單片機(jī)進(jìn)入睡眠狀態(tài)。如需要同時(shí)進(jìn)入兩種工作模式，即PD和IDL同時(shí)為1，則先激活掉電模式。在閑散工作模式狀態(tài)，中央處理器CPU保持睡眠狀態(tài)，而所有片內(nèi)的外設(shè)仍保持激活狀態(tài)，這種方式由軟件產(chǎn)生。此時(shí)，片內(nèi)隨機(jī)存取數(shù)據(jù)存儲(chǔ)器和所有特殊功能寄存器的內(nèi)容保持不變。閑散

17、模式可由任何允許的中斷請(qǐng)求或硬件復(fù)位終止。終止閑散工作模式的方法有兩種，一是任何一條被允許中斷的事件被激活，IDL被硬件清除，即刻終止閑散工作模式。程序會(huì)首先影響中斷，進(jìn)入中斷服務(wù)程序，執(zhí)行完中斷服務(wù)程序，并緊隨RETI指令后，下一條要執(zhí)行的指令就是使單片機(jī)進(jìn)入閑散工作模式，那條指令后面的一條指令。二是通過(guò)硬件復(fù)位也可將閑散工作模式終止。需要注意的是：當(dāng)由硬件復(fù)位來(lái)終止閑散工作模式時(shí)，中央處理器CPU通常是從激活空閑模式那條指令的下一條

18、開(kāi)始繼續(xù)執(zhí)行程序的，要完成內(nèi)部復(fù)位操作</p><p><b>　　掉電模式</b></p><p>　　在掉電模式下，振蕩器停止工作，進(jìn)入掉電模式的指令是最后一條被執(zhí)行的指令，片內(nèi)RAM和特殊功能寄存器的內(nèi)容在中指掉電模式前被凍結(jié)。退出掉電模式的唯一方法是硬件復(fù)位，復(fù)位后將從新定義全部特殊功能寄存器但不改變RAM中的內(nèi)容，在VCC恢復(fù)到正常工作電平前，復(fù)位應(yīng)無(wú)效切必

19、須保持一定時(shí)間以使振蕩器從新啟動(dòng)并穩(wěn)定工作。</p><p>　　閑散和掉電模式外部引腳狀態(tài)。</p><p><b>　　程序存儲(chǔ)器的加密</b></p><p>　　AT89C51可使用對(duì)芯片上的三個(gè)加密位LB1，LB2，LB3進(jìn)行編程（P）或不編程（U）得到如下表所示的功能：</p><p>　　當(dāng)LB1被編程時(shí)，

20、在復(fù)位期間，EA端的電平被鎖存，如果單片機(jī)上電后一直沒(méi)有復(fù)位，鎖存起來(lái)的初始值是一個(gè)不確定數(shù)，這個(gè)不確定數(shù)會(huì)一直保存到真正復(fù)位位置。為了使單片機(jī)正常工作，被鎖存的EA電平與這個(gè)引腳當(dāng)前輯電平一致。機(jī)密位只能通過(guò)整片擦除的方法清除。</p><p>　　Description</p><p>　　The AT89C51 is a low-power, high-performance CMO

21、S 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-sta

22、ndard MCS-51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a mon

23、olithic chip</p><p>　　Function characteristic</p><p>　　The AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five

24、vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two sof

25、tware selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to </p><p>　　Pin Description</p><p>　　VCC：Supply voltage

26、.</p><p>　　GND：Ground.</p><p><b>　　Port 0：</b></p><p>　　Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. Whe

27、n 1s are written to port 0 pins, the pins can be used as highimpedance inputs.Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mod

28、e P0 has internal pullups.Port 0 also receives the code bytes during Flash programming,and outputs the code bytes during programverification. External pullups are requ</p><p><b>　　Port 1</b></

29、p><p>　　Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins they are pulled high by the internal pullups

30、 and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming a

31、nd verification.</p><p><b>　　Port 2</b></p><p>　　Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s ar

32、e written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will source current, because of the internal pullups.Port 2 emit

33、s the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses. In</p><p><b>　　Port 3</b></p><p>　　Po

34、rt 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as

35、inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89C51 as listed below:</p>

36、<p>　　Port 3 also receives some control signals for Flash programming and verification.</p><p><b>　　RST</b></p><p>　　Reset input. A high on this pin for two machine cycles whil

37、e the oscillator is running resets the device.</p><p><b>　　ALE/PROG</b></p><p>　　Address Latch Enable output pulse for latching the low byte of the address during accesses to externa

38、l memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking pu

39、rposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.</p><p>　　If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE

40、 is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.</p><p><b>　　

41、PSEN</b></p><p>　　Program Store Enable is the read strobe to external program memory.When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except

42、that two PSEN activations are skipped during each access to external data memory.</p><p><b>　　EA/VPP</b></p><p>　　External Access Enable. EA must be strapped to GND in order to enabl

43、e the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for in

44、ternal program executions.This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require12-volt VPP.</p><p><b>　　XTAL1</b></p><p>

45、;　　Input to the inverting oscillator amplifier and input to the internal clock operating circuit.</p><p><b>　　XTAL2</b></p><p>　　Output from the inverting oscillator amplifier.</p

46、><p>　　Oscillator Characteristics</p><p>　　XTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Fig

47、ure 1.Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on

48、the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two fli</p><p>　　Figure 1. Oscillator Connections Figure 2. External Clock Dri

49、ve Configuration</p><p><b>　　Idle Mode</b></p><p>　　In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The co

50、ntent of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.It should be noted that when idle is ter

51、minated by a hard ware reset, the device normally resumes program execution,from where it left off, up to two machine cycles before the internal reset</p><p>　　Power-down Mode</p><p>　　In the po

52、wer-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is term

53、inated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be

54、held active long enough to allow the oscillator to </p><p>　　Program Memory Lock Bits</p><p>　　On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obta

55、in the additional features listed in the table below.</p><p>　　When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, t

56、he latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to func