基于at89c52單片機(jī)的交通燈控制系統(tǒng)的設(shè)計(jì)(外文翻譯)

1、<p><b>　　電子與信息工程學(xué)院</b></p><p>　　本科畢業(yè)論文(設(shè)計(jì))</p><p>　　外 文 文 獻(xiàn) 翻 譯</p><p>　　譯文題目： 8-bit Microcontroller With 8K Bytes </p><p>　　Flash AT89C52

2、 </p><p>　　學(xué)生姓名： 吳遠(yuǎn)超 </p><p>　　專 業(yè)： 電氣工程及其自動(dòng)化 </p><p>　　指導(dǎo)教師： 倪 浩

3、 </p><p>　　2012年11月 </p><p><b>　　外文資料</b></p><p>　　8-bit Microcontroller With 8K Bytes Flash AT89C52</p><p><b>　　Features</b></p><

4、p>　　Compatible with MCS-51? Products</p><p>　　8K Bytes of In-System Reprogrammable Flash Memory</p><p>　　Endurance: 1,000 Write/Erase Cycles</p><p>　　Fully Static Operation: 0 Hz

5、 to 24 MHz</p><p>　　Three-level Program Memory Lock</p><p>　　256 x 8-bit Internal RAM</p><p>　　32 Programmable I/O Lines</p><p>　　Three 16-bit Timer/Counters</p>

6、<p>　　Eight Interrupt Sources</p><p>　　Programmable Serial Channel</p><p>　　Low-power Idle and Power-down Modes</p><p>　　Description</p><p>　　The AT89C52 is a low

7、-power, high-performance CMOS 8-bit microcomputer with 8K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is comp

8、atible with the industry-standard 80C51 and 80C52 instruction set and pin out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a v

9、ersatile 8-bit CPU with Flash on a monol</p><p>　　Pin Configurations</p><p>　　Block Diagram</p><p>　　Pin Description</p><p><b>　　VCC</b></p><p>

10、;　　Supply voltage.</p><p><b>　　GND</b></p><p><b>　　Ground.</b></p><p><b>　　Port 0</b></p><p>　　Port 0 is an 8-bit open drain bi-dire

11、ctional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order ad

12、dress/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verificat

13、ion. External pull-ups </p><p><b>　　Port 1</b></p><p>　　Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs.

14、When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal p

15、ull-ups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1</p><p><b>　　Port 2</b></p><p&

16、gt;　　Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can

17、 be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program me

18、mory and during accesses to external data memories that use 16-bi</p><p><b>　　Port 3</b></p><p>　　Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output

19、 buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will sour

20、ce current (IIL) because of the pull-ups.</p><p>　　Port 3 also serves the functions of various special features of the AT89C51, as shown in the following table. Port 3 also receives some control signals for

21、Flash programming and verification.</p><p><b>　　RST</b></p><p>　　Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.</p>

22、<p><b>　　ALE/</b></p><p>　　Address Latch Enable is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input () du

23、ring Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during

24、 each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH.</p><p>　　Program Store Enable is the read strobe to external program memory. When the AT8

25、9C52 is executing code from external program memory, is activated twice each machine cycle, except that two activations are skipped during each access to external data memory.</p><p><b>　　/VPP</b&

26、gt;</p><p>　　External Access Enable. must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit

27、 1 is programmed, will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP ) during Flash programming when 12-v

28、olt programming is selected.</p><p><b>　　XTAL1</b></p><p>　　Input to the inverting oscillator amplifier and input to the internal clock operating circuit.</p><p><b&g

29、t;　　XTAL2</b></p><p>　　Output from the inverting oscillator amplifier.</p><p>　　Special Function Registers</p><p>　　A map of the on-chip memory area called the Special Functio

30、n Register (SFR) space is shown in the Table 1.Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random

31、data, and write accesses will have an indeterminate effect. User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inac

32、t</p><p>　　Timer 2 Registers </p><p>　　Control and status bits are contained in registers T2CON and T2MOD for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Tim

33、er 2 in 16-bit capture mode or 16-bit auto-reload mode.</p><p>　　Interrupt Registers </p><p>　　The individual interrupt enable bits are in the IE register. Two priorities can be set for each of

34、the six interrupt sources in the IP register.</p><p>　　Data Memory</p><p>　　The AT89C52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Fu

35、nction Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space.</p><p>　　When an instruction accesses an internal location above address

36、7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space. For example, the following direct ad

37、dressing instruction accesses the SFR at location 0A0H .</p><p>　　MOV 0A0H, #data</p><p>　　Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following

38、 indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).</p><p>　　MOV @R0, #data</p><p>　　Note that stack operati

39、ons are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.</p><p>　　Timer 0 and 1</p><p>　　Timer 0 and Timer 1 in the AT89C52 operate the same way

40、as Timer 0 and Timer 1 in the AT89C51.</p><p><b>　　Timer 2</b></p><p>　　Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operatio

41、n is selected by bit C/T2 in the SFR T2CON.Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 3.Timer 2 cons

42、ists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator peri</p><p>　　In the Counter function, th

43、e register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high i

44、n one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24

45、 oscillator periods) are required</p><p>　　Capture Mode</p><p>　　In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upo

46、n overflow sets bit TF2 in T2CON.This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1-to-0 transition at external input T2EX also causes the current value in TH2

47、and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like</p><p>　　Auto-reload (Up or Down Counter)</p>&l

48、t;p>　　Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD. Upon reset, the DCEN bit is s

49、et to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin.</p><p>　　Figure 2 shows Timer 2 automatically counting up when DCEN =

50、 0. In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16

51、-bit value in RCAP2H and RCAP2L. The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external inp

52、</p><p>　　Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 3. In this mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count up. The timer w

53、ill overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively. </p><p>　　A logic 0 at T2EX mak

54、es Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers. The EXF2 bit toggles wh

55、enever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt.</p><p><b>　　外文資料譯文：</b></p><p>　　8位8字節(jié)閃存單

56、片機(jī)AT89C52</p><p><b>　　主要性能</b></p><p>　　與MCS-51單片機(jī)產(chǎn)品兼容</p><p>　　8K字節(jié)在系統(tǒng)可編程Flash存儲(chǔ)器</p><p>　　1000次擦寫周期</p><p>　　全靜態(tài)操作：0Hz～24Hz</p><p

57、><b>　　三級(jí)加密程序存儲(chǔ)器</b></p><p>　　256×8位內(nèi)部存儲(chǔ)器</p><p>　　32個(gè)可編程I/O口線</p><p>　　三個(gè)16位定時(shí)器/計(jì)數(shù)器</p><p><b>　　八個(gè)中斷源</b></p><p><b>　

58、　可編程串行通道</b></p><p>　　低功耗空閑和掉電模式</p><p><b>　　功能特性描述</b></p><p>　　AT89S52是一種低功耗、高性能CMOS8位微控制器，具有8K內(nèi)置可編程閃存。產(chǎn)品使用了Atmel公司高密度非易失性存儲(chǔ)器技術(shù)制造，與工業(yè)80C51和80C52產(chǎn)品指令和引腳完全兼容。片上Fla

59、sh允許程序存儲(chǔ)器在系統(tǒng)可編程，亦適于常規(guī)編程器。在單芯片上，擁有靈巧的8位CPU和在系統(tǒng)可編程Flash，使得AT89S52為眾多嵌入式控制應(yīng)用系統(tǒng)提供高靈活、超有效的解決方案。</p><p><b>　　引腳結(jié)構(gòu)</b></p><p><b>　　方框圖</b></p><p><b>　　VCC : 電

60、源</b></p><p><b>　　GND : 地</b></p><p>　　P0口：P0口是一個(gè)8位漏極開路的雙向I/O口。作為輸出口，每位能驅(qū)動(dòng)8個(gè)TTL邏輯電平。對(duì)P0端口寫“1”時(shí)，引腳用作高阻抗輸入。當(dāng)訪問外部程序和數(shù)據(jù)存儲(chǔ)器時(shí)，P0口也被作為低8位地址/數(shù)據(jù)復(fù)用。在這種模式下，P0具有內(nèi)部上拉電阻。在flash編程時(shí)，P0口也用來接收指令

61、字節(jié)；在程序校驗(yàn)時(shí)，輸出指令字節(jié)。程序校驗(yàn)時(shí)，需要外部上拉電阻。</p><p>　　P1口：P1 口是一個(gè)具有內(nèi)部上拉電阻的8位雙向I/O 口，P1 輸出緩沖器能驅(qū)動(dòng)4個(gè)TTL 邏輯電平。對(duì)P1端口寫“1”時(shí)，內(nèi)部上拉電阻把端口拉高，此時(shí)可以作為輸入口使用。作為輸入使用時(shí)，被外部拉低的引腳由于內(nèi)部電阻的原因，將輸出電流（IIL）。此外，P1.0和P1.2分別作定時(shí)器/計(jì)數(shù)器2的外部計(jì)數(shù)輸入（P1.0/T2）和時(shí)

62、器/計(jì)數(shù)器2的觸發(fā)輸入（P1.1/T2EX），具體如下表所示。在flash編程和校驗(yàn)時(shí)，P1口接收低8位地址字節(jié)。</p><p>　　P2 口：P2 口是一個(gè)具有內(nèi)部上拉電阻的8 位雙向I/O 口，P2輸出緩沖器能驅(qū)動(dòng)4個(gè)TTL 邏輯電平。對(duì)P2端口寫“1”時(shí)，內(nèi)部上拉電阻把端口拉高，此時(shí)可以作為輸入口使用。作為輸入使用時(shí)，被外部拉低的引腳由于內(nèi)部電阻的原因，將輸出電流（IIL）。在訪問外部程序存儲(chǔ)器或用16位

63、地址讀取外部數(shù)據(jù)存儲(chǔ)器（例如執(zhí)行MOVX @DPTR）時(shí)，P2口送出高八位地址。在這種應(yīng)用中，P2口使用很強(qiáng)的內(nèi)部上拉發(fā)送1。在使用8位地址（如MOVX @RI）訪問外部數(shù)據(jù)存儲(chǔ)器時(shí)，P2口輸出P2鎖存器的內(nèi)容。在flash編程和校驗(yàn)時(shí)，P2口也接收高8位地址字節(jié)和一些控制信號(hào)。</p><p>　　P3 口：P3口是一個(gè)具有內(nèi)部上拉電阻的8 位雙向I/O 口，p2輸出緩沖器能驅(qū)動(dòng)4個(gè)TTL 邏輯電平。對(duì)P3端口

64、寫“1”時(shí)，內(nèi)部上拉電阻把端口拉高，此時(shí)可以作為輸入口使用。作為輸入使用時(shí)，被外部拉低的引腳由于內(nèi)部電阻的原因，將輸出電流（IIL）。P3口亦作為AT89S52特殊功能（第二功能）使用，如下表所示。在flash編程和校驗(yàn)時(shí)，P3口也接收一些控制信號(hào)。</p><p>　　RST: 復(fù)位輸入。晶振工作時(shí)，RST腳持續(xù)2個(gè)機(jī)器周期高電平將使單片機(jī)復(fù)位。看門狗計(jì)時(shí)完成后，RST腳輸出96個(gè)晶振周期的高電平。特殊寄存器A

65、UXR(地址8EH)上的DISRTO位可以使此功能無效。DISRTO默認(rèn)狀態(tài)下，復(fù)位高電平有效。</p><p>　　ALE/：地址鎖存控制信號(hào)（ALE）是訪問外部程序存儲(chǔ)器時(shí)，鎖存低8位地址的輸出脈沖。在flash編程時(shí)，此引腳（）也用作編程輸入脈沖。</p><p>　　在一般情況下，ALE 以晶振六分之一的固定頻率輸出脈沖，可用來作為外部定時(shí)器或時(shí)鐘使用。然而，特別強(qiáng)調(diào)，在每次訪問外

66、部數(shù)據(jù)存儲(chǔ)器時(shí)，ALE脈沖將會(huì)跳過。如果需要，通過將地址為8EH的SFR的第0位置“1”，ALE操作將無效。這一位置“1”，ALE 僅在執(zhí)行MOVX 或MOVC指令時(shí)有效。否則，ALE 將被微弱拉高。這個(gè)ALE 使能標(biāo)志位（地址為8EH的SFR的第0位）的設(shè)置對(duì)微控制器處于外部執(zhí)行模式下無效。</p><p>　　:外部程序存儲(chǔ)器選通信號(hào)（）是外部程序存儲(chǔ)器選通信號(hào)。</p><p>　　

67、當(dāng) AT89S52從外部程序存儲(chǔ)器執(zhí)行外部代碼時(shí)，在每個(gè)機(jī)器周期被激活兩次，而在訪問外部數(shù)據(jù)存儲(chǔ)器時(shí)，將不被激活。</p><p>　　/VPP:訪問外部程序存儲(chǔ)器控制信號(hào)。為使能從0000H 到FFFFH的外部程序存儲(chǔ)器讀取指令，必須接GND。為了執(zhí)行內(nèi)部程序指令，應(yīng)該接VCC。</p><p>　　在flash編程期間，也接收12伏VPP電壓。</p><p>

68、　　XTAL1:振蕩器反相放大器和內(nèi)部時(shí)鐘發(fā)生電路的輸入端。</p><p>　　XTAL2:振蕩器反相放大器的輸出端。</p><p><b>　　特殊功能寄存器</b></p><p>　　如圖1中所示的存儲(chǔ)器區(qū)域稱為特殊功能寄存器。應(yīng)該注意到，并不是所有的地址都會(huì)被定義，單片機(jī)中那些沒有被定義的地址是無效的。讀訪問這些地址一般會(huì)返回隨機(jī)數(shù)

69、據(jù)，寫訪問這些地址則會(huì)產(chǎn)生一個(gè)不確定的影響。用戶軟件不應(yīng)將那些沒有被列舉出來的地址置1。在這種情況下，復(fù)位后這些單元數(shù)值總是0。</p><p><b>　　定時(shí)/計(jì)數(shù)器2</b></p><p>　　定時(shí)/計(jì)數(shù)器2的控制和狀態(tài)位位于T2CON和T2MOD。寄存器對(duì)（RCAO2H、RCAP2L）是定時(shí)器2在16位捕獲方式或16位自動(dòng)重裝載方式下的捕獲/自動(dòng)重裝載寄存器

70、。</p><p><b>　　中斷寄存器</b></p><p>　　所有單獨(dú)的中斷允許位都存在于中斷允許寄存器IE中。中斷優(yōu)先級(jí)寄存器IP可以為六個(gè)中斷源設(shè)置兩個(gè)中斷優(yōu)先級(jí)。</p><p><b>　　數(shù)據(jù)存儲(chǔ)器</b></p><p>　　AT89C52實(shí)現(xiàn)256字節(jié)片上RAM。高128個(gè)字

71、節(jié)與特殊功能寄存器（SFR）地址是重疊的，也就是高128字節(jié)的RAM和特殊功能寄存器的地址是相同的,但物理上它們是分開的。</p><p>　　當(dāng)一條指令訪問7FH 以上的內(nèi)部地址單元時(shí)，指令中使用的尋址方式是不同的，也即尋址方式?jīng)Q定是訪問高128 字節(jié)RAM 還是訪問特殊功能寄存器。如果指令是直接尋址方式則為訪問特殊功能寄存器。例如，下面的直接尋址指令訪問特殊功能寄存器0A0H（即P2 口）地址單元。 <

72、/p><p>　　MOV 0A0H，#data </p><p>　　間接尋址指令訪問高128 字節(jié)RAM，例如，下面的間接尋址指令中，R0 的內(nèi)容為0A0H，則訪問數(shù)據(jù)字節(jié)地址為0A0H，而不是P2 口（0A0H）。 </p><p>　　MOV @R0，#data </p><p>　　堆棧操作也是間接尋址方式，所以，高128 位數(shù)據(jù)RAM

73、亦可作為堆棧區(qū)使用。</p><p><b>　　定時(shí)器0/定時(shí)器1</b></p><p>　　AT89C52的定時(shí)器0和定時(shí)器1的工作方式與AT89C51相同。</p><p><b>　　定時(shí)器2</b></p><p>　　定時(shí)器2 是一個(gè)16位定時(shí)/計(jì)數(shù)器。它既可當(dāng)定時(shí)器使用，也可作為外部

74、事件計(jì)數(shù)器使用，其工作方式由特殊功能寄存器T2CON（如表3）的C/T2位選擇。定時(shí)器2有三種工作方式：捕獲方式，自動(dòng)重裝載（向上或向下計(jì)數(shù)）方式和波 特率發(fā)生器方式，工作方式由T2CON的控制位來選擇。定時(shí)器2由兩個(gè)8位寄存器TH2和TL2組成，在定時(shí)器工作方式中，每個(gè)機(jī)器周期TL2寄存器的值加1，由于一個(gè)機(jī)器周期由12個(gè)振蕩時(shí)鐘構(gòu)成，因此，計(jì)數(shù)速率為振蕩頻率的1/12。</p><p>　　在計(jì)數(shù)工作方式時(shí)，

75、當(dāng)T2引腳上外部輸入信號(hào)產(chǎn)生由1至0的下降沿時(shí)，寄存器的值加1，在這種工作方式下，每個(gè)機(jī)器周期的5SP2期間，對(duì)外部輸入進(jìn)行采樣。若在第一個(gè)機(jī)器周期中采到的值為1，而在下一個(gè)機(jī)器周期中采到的值為0，則在緊跟著的下一個(gè)周期的S3P1期間寄存器加1。由于識(shí)別1至0的跳變需要2個(gè)機(jī)器周期（24個(gè)振蕩周期），因此，最高計(jì)數(shù)速率為振蕩頻率的1/24。為確保采樣的正確性，要求輸入的電平在變化前至少保持一個(gè)完整周期的時(shí)間，以保證輸入信號(hào)至少被采樣一次

76、。</p><p><b>　　捕獲方式： </b></p><p>　　在捕獲方式下，通過T2CON控制位EXEN2來選擇兩種方式。如果EXEN2=0，定時(shí)器2是一個(gè)16位定時(shí)器或計(jì)數(shù)器，計(jì)數(shù)溢出時(shí)，對(duì)T2CON的溢出標(biāo)志TF2置位，同時(shí)激活中斷。如果EXEN2=1，定時(shí)器2完成相同的操作，而當(dāng)T2EX引腳外部輸入信號(hào)發(fā)生1至0負(fù)跳變時(shí)，也出現(xiàn)TH2 和TL2 中的

77、值分別被捕獲到RCAP2H和RCAP2L中。另外，T2EX引腳信號(hào)的跳變使得T2CON中的EXF2置位，與TF2相仿，EXF2也會(huì)激活中斷。</p><p>　　自動(dòng)重裝載（向上或向下計(jì)數(shù)器）方式： </p><p>　　當(dāng)定時(shí)器2工作于16位自動(dòng)重裝載方式時(shí)，能對(duì)其編程為向上或向下計(jì)數(shù)方式，這個(gè)功能可通過特殊功能寄存器T2CON的DCEN位（允許向下計(jì)數(shù)）來選擇的。復(fù)位時(shí)，DCEN位置“

78、0”，定時(shí)器2 默認(rèn)設(shè)置為向上計(jì)數(shù)。當(dāng)DCEN置位時(shí)，定時(shí)器2既可向上計(jì)數(shù)也可向下計(jì)數(shù)，這取決于T2EX引腳的值。</p><p>　　當(dāng)DCEN=0時(shí)，定時(shí)器2自動(dòng)設(shè)置為向上計(jì)數(shù)，在這種方式下，T2CON 中的EXEN2 控制位有兩種選擇，若EXEN2=0，定時(shí)器2為向上計(jì)數(shù)至0FFFFH溢出，置位TF2 激活中斷，同時(shí)把16 位計(jì)數(shù)寄存器RCAP2H 和RCAP2L重裝載，RCAP2H 和RCAP2L 的值可

79、由軟件預(yù)置。若EXEN2=1，定時(shí)器2的16位重裝載由溢出或外部輸入端T2EX從1至0的下降沿觸發(fā)。這個(gè)脈沖使EXF2置位，如果中斷允許，同樣產(chǎn)生中斷。定時(shí)器2 的中斷入口地址是：002BH ——0032H 。 </p><p>　　當(dāng)DCEN=1時(shí)，允許定時(shí)器2向上或向下計(jì)數(shù)，如圖6所示。這種方式下，T2EX引腳控制計(jì)數(shù)器方向。T2EX引腳為邏輯“1”時(shí)，定時(shí)器向上計(jì)數(shù)，當(dāng)計(jì)數(shù)0FFFFH向上溢出時(shí)，置位TF2